Issued Patents All Time
Showing 251–275 of 437 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10217863 | Fabrication of a vertical fin field effect transistor with an asymmetric gate structure | Shogo Mochizuki | 2019-02-26 |
| 10217840 | Replacement metal gate structures | Veeraraghavan S. Basker, Kangguo Cheng, Theodorus E. Standaert | 2019-02-26 |
| 10211316 | Silicidation of bottom source/drain sheet using pinch-off sacrificial spacer process | Brent A. Anderson, Huiming Bu, Terence B. Hook, Fee Li Lie | 2019-02-19 |
| 10177256 | Replacement metal gate structures | Veeraraghavan S. Basker, Kangguo Cheng, Theodorus E. Standaert | 2019-01-08 |
| 10170540 | Capacitors | Veeraraghavan S. Basker, Kangguo Cheng, Christopher J. Penny, Theodorus E. Standaert | 2019-01-01 |
| 10170425 | Microstructure of metal interconnect layer | Hong He, Juntao Li, Chih-Chao Yang | 2019-01-01 |
| 10164060 | Work function metal fill for replacement gate fin field effect transistor process | Hong He, Yongan Xu, Yunpeng Yin | 2018-12-25 |
| 10157797 | FinFET devices | Veeraraghavan S. Basker, Kangguo Cheng, Theodorus E. Standaert | 2018-12-18 |
| 10157912 | CMOS compatible fuse or resistor using self-aligned contacts | Veeraraghavan S. Basker, Kangguo Cheng, Theodorus E. Standaert | 2018-12-18 |
| 10147803 | Work function metal fill for replacement gate fin field effect transistor process | Hong He, Yongan Xu, Yunpeng Yin | 2018-12-04 |
| 10141426 | Vertical transistor device | Brent A. Anderson, Huiming Bu, Fee Li Lie, Shogo Mochizuki | 2018-11-27 |
| 10141402 | FinFET devices | Veeraraghavan S. Basker, Kangguo Cheng, Theodorus E. Standaert | 2018-11-27 |
| 10103065 | Gate metal patterning for tight pitch applications | Shogo Mochizuki, Alexander Reznicek, Joshua M. Rubin | 2018-10-16 |
| 10096484 | Vertical transistor with a body contact for back-biasing | Veeraraghavan S. Basker, Kangguo Cheng, Theodorus E. Standaert | 2018-10-09 |
| 10090302 | Self-aligned shallow trench isolation and doping for vertical fin transistors | Brent A. Anderson, Fee Li Lie | 2018-10-02 |
| 10090202 | Source and drain epitaxial semiconductor material integration for high voltage semiconductor devices | Balasubramanian Pranatharthiharan, Ruilong Xie | 2018-10-02 |
| 10090411 | Air-gap top spacer and self-aligned metal gate for vertical fets | Veeraraghavan S. Basker, Kangguo Cheng, Theodorus E. Standaert | 2018-10-02 |
| 10084065 | Reducing resistance of bottom source/drain in vertical channel devices | Shogo Mochizuki | 2018-09-25 |
| 10083862 | Protective liner between a gate dielectric and a gate contact | Lawrence A. Clevenger, Baozhen Li, Kirk D. Peterson | 2018-09-25 |
| 10079232 | FinFET CMOS with silicon fin n-channel FET and silicon germanium fin p-channel FET | Veeraraghavan S. Basker, Kangguo Cheng, Theodorus E. Standaert | 2018-09-18 |
| 10074577 | Silicon germanium and silicon fins on oxide from bulk wafer | Hong He, James Kuss, Nicolas Loubet | 2018-09-11 |
| 10068807 | Uniform shallow trench isolation | Kangguo Cheng, Peng Xu, Chen Zhang | 2018-09-04 |
| 10068970 | Nanowire isolation scheme to reduce parasitic capacitance | Kangguo Cheng, Bruce B. Doris | 2018-09-04 |
| 10062783 | Silicon germanium fin channel formation | Hong He, Nicolas Loubet | 2018-08-28 |
| 10062785 | Fin field-effect transistor (FinFET) with reduced parasitic capacitance | Veeraraghavan S. Basker, Kangguo Cheng, Theodorus E. Standaert | 2018-08-28 |