Issued Patents All Time
Showing 26–50 of 52 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10216882 | Critical path straightening system based on free-space aware and timing driven incremental placement | Jinwook Jung, Frank J. Musante, Gi-Joon Nam, Shyam Ramji, Lakshmi N. Reddy +1 more | 2019-02-26 |
| 9245076 | Orthogonal circuit element routing | Vassilios Gerousis, Lars Liebmann, Stefanus Mantik, Shuo Zhang | 2016-01-26 |
| 9158885 | Reducing color conflicts in triple patterning lithography | Michael S. Gray, Matthew T. Guzowski, Alexander Ivrii, Lars Liebmann, Kevin W. McCullen +1 more | 2015-10-13 |
| 8938702 | Timing driven routing for noise reduction in integrated circuit design | Andre Hogan, Andrew D. Huber, Zhuo Li, Karsten Muuss, Sven Peyer +1 more | 2015-01-20 |
| 8631375 | Via selection in integrated circuit design | Robert R. Arelt, Jeanne P. Bickford, Andrew D. Huber, Karl W. Vinson, Tina Wagner | 2014-01-14 |
| 8448110 | Method to reduce delay variation by sensitivity cancellation | Peter A. Habitz, Eric A. Foreman | 2013-05-21 |
| 8347257 | Detailed routability by cell placement | Charles J. Alpert, Andrew D. Huber, Zhuo Li, Gi-Joon Nam, Shyam Ramji +4 more | 2013-01-01 |
| 8230378 | Method for IC wiring yield optimization, including wire widening during and after routing | John M. Cohn, Jason D. Hibbeler | 2012-07-24 |
| 7961932 | Method and apparatus for manufacturing diamond shaped chips | Robert J. Allen, John M. Cohn, Scott Whitney Gould, Peter A. Habitz, Juergen Koehl +2 more | 2011-06-14 |
| 7895545 | Methods for designing a product chip a priori for design subsetting, feature analysis, and yield learning | John M. Cohn, Leah Pastel | 2011-02-22 |
| 7725864 | Systematic yield in semiconductor manufacture | Paul H. Bergeron, Jason D. Hibbeler | 2010-05-25 |
| 7721240 | Systematic yield in semiconductor manufacture | Paul H. Bergeron, Jason D. Hibbeler | 2010-05-18 |
| 7657859 | Method for IC wiring yield optimization, including wire widening during and after routing | John M. Cohn, Jason D. Hibbeler | 2010-02-02 |
| 7337415 | Systematic yield in semiconductor manufacture | Paul H. Bergeron, Jason D. Hibbeler | 2008-02-26 |
| 7289659 | Method and apparatus for manufacturing diamond shaped chips | Robert J. Allen, John M. Cohn, Scott Whitney Gould, Peter A. Habitz, Juergen Koehl +2 more | 2007-10-30 |
| 7117456 | Circuit area minimization using scaling | Michael S. Gray, Kevin W. McCullen, Robert F. Walker | 2006-10-03 |
| 7076749 | Method and system for improving integrated circuit manufacturing productivity | Douglas W. Kemerer, Daniel N. Maynard, Lijiang Wang, Peter S. Wissell | 2006-07-11 |
| 7062729 | Method and system for obtaining a feasible integer solution from a half-integer solution in hierarchical circuit layout optimization | Michael S. Gray, Jason D. Hibbeler, Robert F. Walker | 2006-06-13 |
| 6993692 | Method, system and apparatus for aggregating failures across multiple memories and applying a common defect repair solution to all of the multiple memories | Michael R. Ouellette, Paul S. Zuchowski | 2006-01-31 |
| 6986109 | Practical method for hierarchical-preserving layout optimization of integrated circuit layout | Robert J. Allen, Fook-Luen Heng, Alexey Y. Lvov, Kevin W. McCullen, Sriram Peri | 2006-01-10 |
| 6941528 | Use of a layout-optimization tool to increase the yield and reliability of VLSI designs | Robert J. Allen, Jason D. Hibbeler | 2005-09-06 |
| 6904575 | Method for improving chip yields in the presence of via flaring | Robert J. Allen | 2005-06-07 |
| 6738954 | Method for prediction random defect yields of integrated circuits with accuracy and computation time controls | Archibald J. Allen, Wilm E. Donath, Alan Dziedzic, Mark A. Lavin, Daniel N. Maynard +1 more | 2004-05-18 |
| 6305004 | Method for improving wiring related yield and capacitance properties of integrated circuits by maze-routing | Gary R. Doyle, Philip S. Honsinger, Steven G. Lovejoy, Charles L. Meiley, Gorden Seth Starkey, Jr. +1 more | 2001-10-16 |
| 6301690 | Method to improve integrated circuit defect limited yield | Gary S. Ditlow, Daria R. Dooling, David E. Moran, Richard L. Moore, Ralph J. Williams +1 more | 2001-10-09 |