Issued Patents All Time
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6305004 | Method for improving wiring related yield and capacitance properties of integrated circuits by maze-routing | Gustavo E. Tellez, Gary R. Doyle, Philip S. Honsinger, Steven G. Lovejoy, Gorden Seth Starkey, Jr. +1 more | 2001-10-16 |
| 6266802 | Detailed grid point layout using a massively parallel logic including an emulator/simulator paradigm | Richard L. Malm, Frank Albert Nemec, II | 2001-07-24 |
| 5673201 | Sub-problem extraction method for wiring localized congestion areas in VLSI wiring design | Richard L. Malm | 1997-09-30 |
| 5043920 | Multi-dimension visual analysis | Richard L. Malm | 1991-08-27 |