GS

Ghavam G. Shahidi

IBM: 349 patents #52 of 70,183Top 1%
Globalfoundries: 26 patents #104 of 4,424Top 3%
ET Elpis Technologies: 2 patents #16 of 121Top 15%
FS Freeescale Semiconductor: 1 patents #2,021 of 3,767Top 55%
📍 Pound Ridge, NY: #1 of 77 inventorsTop 2%
🗺 New York: #37 of 115,490 inventorsTop 1%
Overall (All Time): #743 of 4,157,543Top 1%
377
Patents All Time

Issued Patents All Time

Showing 351–375 of 377 patents

Patent #TitleCo-InventorsDate
6828630 CMOS device on ultrathin SOI with a deposited raised source/drain, and a method of manufacture Heemyong Park, Byoung Hun Lee, Paul D. Agnello, Dominic J. Schepis 2004-12-07
6800518 Formation of patterned silicon-on-insulator (SOI)/silicon-on-nothing (SON) composite structure by porous Si engineering Robert E. Bendernagel, Kwang Su Choe, Bijan Davari, Keith E. Fogel, Devendra K. Sadana +1 more 2004-10-05
6756257 Patterned SOI regions on semiconductor chips Bijan Davari, Devendra K. Sadana, Sandip Tiwari 2004-06-29
6686629 SOI MOSFETS exhibiting reduced floating-body effects Fariborz Assaderaghi, Werner Rausch, Dominic J. Schepis 2004-02-03
6657261 Ground-plane device with back oxide topography Fariborz Assaderaghi, Tze-Chiang Chen, K. Paul Muller, Edward J. Nowak, Devendra K. Sadana 2003-12-02
6653698 Integration of dual workfunction metal gate CMOS devices Byoung Hun Lee, Effendi Leobandung 2003-11-25
6645795 Polysilicon doped transistor using silicon-on-insulator and double silicon-on-insulator K. Paul Muller, Dominic J. Schepis 2003-11-11
6635517 Use of disposable spacer to introduce gettering in SOI layer Tze-Chiang Chen, Thomas T. Hwang, Mukesh V. Khare, Effendi Leobandung, Anda C. Mocuta +1 more 2003-10-21
6566177 Silicon-on-insulator vertical array device trench capacitor DRAM Carl Radens, Gary B. Bronner, Tze-Chiang Chen, Bijan Davari, Jack A. Mandelman +3 more 2003-05-20
6566198 CMOS structure with non-epitaxial raised source/drain and self-aligned gate and method of manufacture Heemyong Park, Fariborz Assaderaghi, Atul Ajmera 2003-05-20
6562666 Integrated circuits with reduced substrate capacitance Heemyong Park, Fariborz Assaderaghi, Jack A. Mandelman, Lawrence F. Wagner, Jr. 2003-05-13
6541317 Polysilicon doped transistor K. Paul Muller, Dominic J. Schepis 2003-04-01
6521947 Method of integrating substrate contact on SOI wafers with STI process Atul Ajmera, Effendi Leobandung, Werner Rausch, Dominic J. Schepis 2003-02-18
6521949 SOI transistor with polysilicon seed Fariborz Assaderaghi, Tze-Chiang Chen, K. Paul Muller, Edward J. Nowak 2003-02-18
6432754 Double SOI device with recess etch and epitaxy Fariborz Assaderaghi, Tze-Chiang Chen, K. Paul Muller, Edward J. Nowak, Devendra K. Sadana 2002-08-13
6429488 Densely patterned silicon-on-insulator (SOI) region on a wafer Effendi Leobandung, Devendra K. Sadana, Dominic J. Schepis 2002-08-06
6426252 Silicon-on-insulator vertical array DRAM cell with self-aligned buried strap Carl Radens, Gary B. Bronner, Tze-Chiang Chen, Bijan Davari, Jack A. Mandelman +3 more 2002-07-30
6404014 Planar and densely patterned silicon-on-insulator structure Effendi Leobandung, Devendra K. Sadana, Dominic J. Schepis 2002-06-11
6337253 Process of making buried capacitor for silicon-on-insulator structure Bijan Davari, Effendi Leobandung, Werner Rausch 2002-01-08
6333532 Patterned SOI regions in semiconductor chips Bijan Davari, Devendra K. Sadana, Sandip Tiwari 2001-12-25
6214694 Process of making densely patterned silicon-on-insulator (SOI) region on a wafer Effendi Leobandung, Devendra K. Sadana, Dominic J. Schepis 2001-04-10
6188122 Buried capacitor for silicon-on-insulator structure Bijan Davari, Effendi Leobandung, Werner Rausch 2001-02-13
6180486 Process of fabricating planar and densely patterned silicon-on-insulator structure Effendi Leobandung, Devendra K. Sadana, Dominic J. Schepis 2001-01-30
6131182 Method and apparatus for synthesizing and optimizing control logic based on SRCMOS logic array macros Michael P. Beakes, Barbara Alana Chappell, Terry I. Chappell, Gary S. Ditlow, Barry Lee Dorfman +5 more 2000-10-10
5811857 Silicon-on-insulator body-coupled gated diode for electrostatic discharge (ESD) and analog applications Fariborz Assaderaghi, Louis L. Hsu, Jack A. Mandelman, Steven H. Voldman 1998-09-22