Issued Patents All Time
Showing 301–325 of 377 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8318574 | SOI trench DRAM structure with backside strap | Bruce B. Doris, Kangguo Cheng, Ali Khakifirooz, Pranita Kulkarni | 2012-11-27 |
| 8304301 | Implant free extremely thin semiconductor devices | Kangguo Cheng, Bruce B. Doris, Dechao Guo, Pranita Kulkarni, Philip J. Oldiges | 2012-11-06 |
| 8293615 | Self-aligned dual depth isolation and method of fabrication | Kangguo Cheng, Robert H. Dennard, Bruce B. Doris, Ali Khakifirooz | 2012-10-23 |
| 8278175 | Compressively stressed FET device structures | Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz, Pranita Kulkarni | 2012-10-02 |
| 8263468 | Thin body semiconductor devices | Thomas N. Adam, Kangguo Cheng, Ali Khakifirooz, Alexander Reznicek, Devendra K. Sadana | 2012-09-11 |
| 8207038 | Stressed Fin-FET devices with low contact resistance | Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz, Pranita Kulkarni | 2012-06-26 |
| 8202767 | Device and method of reducing junction leakage | Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz, Pranita Kulkarni | 2012-06-19 |
| 8169025 | Strained CMOS device, circuit and method of fabrication | Stephen W. Bedell, Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz, Devendra K. Sadana | 2012-05-01 |
| 8169024 | Method of forming extremely thin semiconductor on insulator (ETSOI) device without ion implantation | Kangguo Cheng, Bruce B. Doris, Pranita Kulkarni | 2012-05-01 |
| 8138543 | Hybrid FinFET/planar SOI FETs | Kangguo Cheng, Bruce B. Doris | 2012-03-20 |
| 8093099 | Lock and key through-via method for wafer level 3D integration and structures produced | Sampath Purushothaman, Mary E. Rothwell, Roy R. Yu | 2012-01-10 |
| 8084309 | Extremely thin silicon on insulator (ETSOI) complementary metal oxide semiconductor (CMOS) with in-situ doped source and drain regions formed by a single mask | Kangguo Cheng, Bruce B. Doris | 2011-12-27 |
| 8080838 | Contact scheme for FINFET structures with multiple FINs | Leland Chang, Wilfried E. Haensch, Meikei Ieong, Huiling Shang | 2011-12-20 |
| 8053759 | Ion implantation for suppression of defects in annealed SiGe layers | Stephen W. Bedell, Huajie Chen, Keith E. Fogel, Devendra K. Sadana | 2011-11-08 |
| 8021956 | Ultrathin SOI CMOS devices employing differential STI liners | Zhibin Ren, Dinkar Singh, Jeffrey W. Sleight, Xinhui Wang | 2011-09-20 |
| 8022488 | High-performance FETs with embedded stressors | Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz | 2011-09-20 |
| 8008138 | Extremely thin semiconductor on insulator semiconductor device with suppressed dopant segregation | Kangguo Cheng, Bruce B. Doris | 2011-08-30 |
| 7968459 | Ion implantation combined with in situ or ex situ heat treatment for improved field effect transistors | Stephen W. Bedell, Joel P. Desouza, Zhibin Ren, Alexander Reznicek, Devandra K. Sadana +1 more | 2011-06-28 |
| 7964896 | Buried channel MOSFET using III-V compound semiconductors and high k gate dielectrics | Edward W. Kiewra, Steven J. Koester, Devendra K. Sadana, Yanning Sun | 2011-06-21 |
| 7897444 | Strained semiconductor-on-insulator (sSOI) by a simox method | Thomas N. Adam, Stephen W. Bedell, Joel P. de Souza, Keith E. Fogel, Alexander Reznicek +1 more | 2011-03-01 |
| 7855455 | Lock and key through-via method for wafer level 3 D integration and structures produced | Sampath Purushothaman, Mary E. Rothwell, Roy R. Yu | 2010-12-21 |
| 7785999 | Formation of fully silicided metal gate using dual self-aligned silicide process | Cyril Cabral, Jr., Chester T. Dziobkowski, Sunfei Fang, Evgeni Gousev, Rajarao Jammy +4 more | 2010-08-31 |
| 7759772 | Method to form Si-containing SOI and underlying substrate with different orientations | Meikei Ieong, Devendra K. Sadana | 2010-07-20 |
| 7749869 | Crystalline silicon substrates with improved minority carrier lifetime including a method of annealing and removing SiOx precipitates and getterning sites | Joel P. de Souza, Harold J. Hovel, Daniel A. Inns, Devendra K. Sadana | 2010-07-06 |
| 7682917 | Disposable metallic or semiconductor gate spacer | Stephen W. Bedell, Michael P. Chudzik, William K. Henson, Naim Moumen, Vijay Narayanan +2 more | 2010-03-23 |