Issued Patents All Time
Showing 476–496 of 496 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6858903 | MOSFET device with in-situ doped, raised source and drain structures | Wesley C. Natzle, Marc W. Cantell, Louis D. Lanzerotti, Brian L. Tessier, Ryan Wuthrich | 2005-02-22 |
| 6825097 | Triple oxide fill for trench isolation | Klaus D. Beyer, Patricia A. O'Neil, Deborah Ryan, Peter Smeys | 2004-11-30 |
| 6800530 | Triple layer hard mask for gate patterning to fabricate scaled CMOS transistors | Byoung Hun Lee, Bachir Dirahoui, Tai-chi Su | 2004-10-05 |
| 6774000 | Method of manufacture of MOSFET device with in-situ doped, raised source and drain structures | Wesley C. Natzle, Marc W. Cantell, Louis D. Lanzerotti, Brian L. Tessier, Ryan Wuthrich | 2004-08-10 |
| 6660596 | Double planar gated SOI MOSFET structure | James W. Adkisson, John A. Bracchitta, John J. Ellis-Monaghan, Jerome B. Lasky, Kirk D. Peterson +1 more | 2003-12-09 |
| 6653698 | Integration of dual workfunction metal gate CMOS devices | Byoung Hun Lee, Ghavam G. Shahidi | 2003-11-25 |
| 6649460 | Fabricating a substantially self-aligned MOSFET | — | 2003-11-18 |
| 6635517 | Use of disposable spacer to introduce gettering in SOI layer | Tze-Chiang Chen, Thomas T. Hwang, Mukesh V. Khare, Anda C. Mocuta, Paul A. Ronsheim +1 more | 2003-10-21 |
| 6521947 | Method of integrating substrate contact on SOI wafers with STI process | Atul Ajmera, Werner Rausch, Dominic J. Schepis, Ghavam G. Shahidi | 2003-02-18 |
| 6483156 | Double planar gated SOI MOSFET structure | James W. Adkisson, John A. Bracchitta, John J. Ellis-Monaghan, Jerome B. Lasky, Kirk D. Peterson +1 more | 2002-11-19 |
| 6437400 | Shallow trench isolation on a silicon substrate using nitrogen implant into the side wall | — | 2002-08-20 |
| 6429488 | Densely patterned silicon-on-insulator (SOI) region on a wafer | Devendra K. Sadana, Dominic J. Schepis, Ghavam G. Shahidi | 2002-08-06 |
| 6404014 | Planar and densely patterned silicon-on-insulator structure | Devendra K. Sadana, Dominic J. Schepis, Ghavam G. Shahidi | 2002-06-11 |
| 6352906 | Nitridization of STI sidewalls | — | 2002-03-05 |
| 6339005 | Disposable spacer for symmetric and asymmetric Schottky contact to SOI MOSFET | Andres Bryant, Jerome B. Lasky, Dominic J. Schepis | 2002-01-15 |
| 6337253 | Process of making buried capacitor for silicon-on-insulator structure | Bijan Davari, Werner Rausch, Ghavam G. Shahidi | 2002-01-08 |
| 6238998 | Shallow trench isolation on a silicon substrate using nitrogen implant into the side wall | — | 2001-05-29 |
| 6214694 | Process of making densely patterned silicon-on-insulator (SOI) region on a wafer | Devendra K. Sadana, Dominic J. Schepis, Ghavam G. Shahidi | 2001-04-10 |
| 6188122 | Buried capacitor for silicon-on-insulator structure | Bijan Davari, Werner Rausch, Ghavam G. Shahidi | 2001-02-13 |
| 6180486 | Process of fabricating planar and densely patterned silicon-on-insulator structure | Devendra K. Sadana, Dominic J. Schepis, Ghavam G. Shahidi | 2001-01-30 |
| 6069380 | Single-electron floating-gate MOS memory | Stephen Y. Chou, Lingjie Jay Guo | 2000-05-30 |