Issued Patents All Time
Showing 101–125 of 408 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9418903 | Structure and method for effective device width adjustment in finFET devices using gate workfunction shift | Ramachandra Divakaruni, Arvind Kumar | 2016-08-16 |
| 9406888 | Carbon nanotube device | Lawrence A. Clevenger, Chandrasekhar Narayan, Gregory A. Northrop, Brian C. Sapp | 2016-08-02 |
| 9391020 | Interconnect structure having large self-aligned vias | John H. Zhang, Lawrence A. Clevenger, Yiheng Xu, Richard S. Wise, Akil Khamisi Sutton +2 more | 2016-07-12 |
| 9385177 | Technique for fabrication of microelectronic capacitors and resistors | John H. Zhang, Lawrence A. Clevenger, Yiheng Xu, Edem Wornyo | 2016-07-05 |
| 9348680 | Statistical design with importance sampling reuse | Rajiv V. Joshi, Rouwaida N. Kanj, Sani R. Nassif | 2016-05-24 |
| 9337087 | Multilayer structure in an integrated circuit for damage prevention and detection and methods of creating the same | John H. Zhang, Lawrence A. Clevenger, Yiheng Xu, Byoung Youp Kim, Walter Kleemeier | 2016-05-10 |
| 9324793 | Method for controlling the profile of an etched metallic layer | Lawrence A. Clevenger, Richard S. Wise, Edem Wornyo, Yiheng Xu, John H. Zhang | 2016-04-26 |
| 9305930 | Finfet crosspoint flash memory | Ramachandra Divakaruni, Arvind Kumar | 2016-04-05 |
| 9257433 | Structure and method of forming enhanced array device isolation for implanted plate EDRAM | Herbert L. Ho, Naoyoshi Kusaba, Karen A. Nummy, Ravi M. Todi, Geng Wang | 2016-02-09 |
| 9240375 | Modular fuses and antifuses for integrated circuits | John H. Zhang, Lawrence A. Clevenger, Yiheng Xu, Edem Wornyo | 2016-01-19 |
| 9214429 | Trench interconnect having reduced fringe capacitance | John H. Zhang, Hsueh-Chung Chen, Lawrence A. Clevenger, Yann Mignot, Richard S. Wise +2 more | 2015-12-15 |
| 9209036 | Method for controlling the profile of an etched metallic layer | Lawrence A. Clevenger, Richard S. Wise, Edem Wornyo, Yiheng Xu, John H. Zhang | 2015-12-08 |
| 9196707 | Oxygen scavenging spacer for a gate electrode | Michael P. Chudzik, Deleep R. Nair, Vijay Narayanan, Jay M. Shah | 2015-11-24 |
| 9147031 | Analysis of chip-mean variation and independent intra-die variation for chip yield determination | Amith Singhee | 2015-09-29 |
| 9089080 | Corrugated interfaces for multilayered interconnects | Lawrence A. Clevenger, Timothy J. Dalton, Elbert E. Huang, Sampath Purushothaman | 2015-07-21 |
| 9087784 | Structure and method of Tinv scaling for high k metal gate technology | Michael P. Chudzik, Dechao Guo, Siddarth A. Krishnan, Unoh Kwon, Shahab Siddiqui | 2015-07-21 |
| 9082625 | Patterning through imprinting | Lawrence A. Clevenger, Richard S. Wise, Yiheng Xu, John H. Zhang | 2015-07-14 |
| 9059320 | Structure and method of forming enhanced array device isolation for implanted plate EDRAM | Herbert L. Ho, Naoyoshi Kusaba, Karen A. Nummy, Ravi M. Todi, Geng Wang | 2015-06-16 |
| 9059211 | Oxygen scavenging spacer for a gate electrode | Michael P. Chudzik, Deleep R. Nair, Vijay Narayanan, Jay M. Shah | 2015-06-16 |
| 9059000 | Methods and structures for protecting one area while processing another area on a chip | Deok-kee Kim, Kenneth T. Settlemyer, Jr., Kangguo Cheng, Ramachandra Divakaruni, Dirk Pfeiffer +4 more | 2015-06-16 |
| 9040369 | Structure and method for replacement gate MOSFET with self-aligned contact using sacrificial mandrel dielectric | Shahab Siddiqui, Michael P. Chudzik | 2015-05-26 |
| 9030295 | RFID tag with environmental sensor | Ira L. Allen, Lawrence A. Clevenger, Kevin S. Petrarca | 2015-05-12 |
| 9018092 | Encapsulated metal interconnect | John H. Zhang, Lawrence A. Clevenger, Yiheng Xu | 2015-04-28 |
| 9006837 | Structure and method of Tinv scaling for high k metal gate technology | Michael P. Chudzik, Dechao Guo, Siddarth A. Krishnan, Unoh Kwon, Shahab Siddiqui | 2015-04-14 |
| 8969163 | Forming facet-less epitaxy with self-aligned isolation | Michael V. Aquilino, Byeong Y. Kim, Ying Li | 2015-03-03 |