Issued Patents All Time
Showing 51–75 of 408 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10734289 | Method for forming strained fin channel devices | Kangguo Cheng, Junli Wang, Lawrence A. Clevenger, John H. Zhang | 2020-08-04 |
| 10727122 | Self-aligned via interconnect structures | Benjamin C. Backes, Brian Alexander Cohen, Joyeeta Nag | 2020-07-28 |
| 10707224 | FinFET vertical flash memory | Ramachandra Divakaruni, Arvind Kumar | 2020-07-07 |
| 10700214 | Overturned thin film device with self-aligned gate and source/drain (S/D) contacts | Lawrence A. Clevenger, Yiheng Xu, John H. Zhang | 2020-06-30 |
| 10546743 | Advanced interconnect with air gap | John H. Zhang, Yann Mignot, Lawrence A. Clevenger, Richard S. Wise, Yiheng Xu +2 more | 2020-01-28 |
| 10546936 | Structure for reduced source and drain contact to gate stack capacitance | Richard Q. Williams | 2020-01-28 |
| 10516064 | Multiple width nanosheet devices | Kangguo Cheng, Lawrence A. Clevenger, Junli Wang, John H. Zhang | 2019-12-24 |
| 10438850 | Semiconductor device with local connection | Kangguo Cheng, Lawrence A. Clevenger, Junli Wang, John H. Zhang | 2019-10-08 |
| 10431495 | Semiconductor device with local connection | Kangguo Cheng, Lawrence A. Clevenger, Junli Wang, John H. Zhang | 2019-10-01 |
| 10411128 | Strained fin channel devices | Kangguo Cheng, Junli Wang, Lawrence A. Clevenger, John H. Zhang | 2019-09-10 |
| 10395984 | Self-aligned via interconnect structures | Benjamin C. Backes, Brian Alexander Cohen, Joyeeta Nag | 2019-08-27 |
| 10387235 | Statistical design with importance sampling reuse | Rajiv V. Joshi, Rouwaida N. Kanj, Sani R. Nassif | 2019-08-20 |
| 10388639 | Self-aligned three dimensional chip stack and method for making the same | Lawrence A. Clevenger, Yiheng Xu, John H. Zhang | 2019-08-20 |
| 10374046 | Structure for reduced source and drain contact to gate stack capacitance | Richard Q. Williams | 2019-08-06 |
| 10347617 | Self-aligned three dimensional chip stack and method for making the same | Lawrence A. Clevenger, Yiheng Xu, John H. Zhang | 2019-07-09 |
| 10325778 | Utilizing multiple layers to increase spatial frequency | Lawrence A. Clevenger, John H. Zhang | 2019-06-18 |
| 10325777 | Utilizing multiple layers to increase spatial frequency | Lawrence A. Clevenger, John H. Zhang | 2019-06-18 |
| 10319870 | Photovoltaic module with a controllable infrared protection layer | Lawrence A. Clevenger, Timothy J. Dalton, Maxime Darnon, Rainer Krause, Gerd Pfeiffer +2 more | 2019-06-11 |
| 10319630 | Encapsulated damascene interconnect structure for integrated circuits | John H. Zhang, Lawrence A. Clevenger, Yiheng Xu | 2019-06-11 |
| 10304815 | Self-aligned three dimensional chip stack and method for making the same | Lawrence A. Clevenger, Yiheng Xu, John H. Zhang | 2019-05-28 |
| 10269905 | Structure for reduced source and drain contact to gate stack capacitance | Richard Q. Williams | 2019-04-23 |
| 10242911 | Forming self-aligned vias and air-gaps in semiconductor fabrication | Lawrence A. Clevenger, John H. Zhang | 2019-03-26 |
| 10157832 | Integrated circuit structure including via interconnect structure abutting lateral ends of metal lines and methods of forming same | John H. Zhang, Lawrence A. Clevenger | 2018-12-18 |
| 10115633 | Method for producing self-aligned line end vias and related device | John H. Zhang, Lawrence A. Clevenger | 2018-10-30 |
| 10026849 | Structure and process for overturned thin film device with self-aligned gate and S/D contacts | Lawrence A. Clevenger, Yiheng Xu, John H. Zhang | 2018-07-17 |