Issued Patents All Time
Showing 26–50 of 408 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11742836 | Random number generator using cross-coupled ring oscillators | Kangguo Cheng | 2023-08-29 |
| 11696518 | Hybrid non-volatile memory cell | Kangguo Cheng, Ruilong Xie, Juntao Li | 2023-07-04 |
| 11690305 | Phase change memory cell with an airgap to allow for the expansion and restriction of the PCM material | Kangguo Cheng, Ruilong Xie, Juntao Li | 2023-06-27 |
| 11683998 | Vertical phase change bridge memory cell | Juntao Li, Kangguo Cheng, Ruilong Xie | 2023-06-20 |
| 11652156 | Nanosheet transistor with asymmetric gate stack | Ruilong Xie, Kangguo Cheng, Juntao Li, Dechao Guo, Tao Li +1 more | 2023-05-16 |
| 11645206 | Distributed memory-augmented neural network architecture | Ahmet S. Ozcan, Tomasz Kornuta, Nicolas Antoine | 2023-05-09 |
| 11588104 | Resistive memory with vertical transport transistor | Kangguo Cheng, Ruilong Xie, Juntao Li | 2023-02-21 |
| 11380583 | Forming self-aligned vias and air-gaps in semiconductor fabrication | Lawrence A. Clevenger, John H. Zhang | 2022-07-05 |
| 11372701 | Statistical design with importance sampling reuse | Rajiv V. Joshi, Rouwaida N. Kanj, Sani R. Nassif | 2022-06-28 |
| 11349001 | Replacement gate cross-couple for static random-access memory scaling | Ruilong Xie, Kangguo Cheng, Veeraraghavan S. Basker, Juntao Li | 2022-05-31 |
| 11348832 | Self-aligned via interconnect structures | Benjamin C. Backes, Brian Alexander Cohen, Joyeeta Nag | 2022-05-31 |
| 11322402 | Self-aligned top via scheme | Ruilong Xie, Chih-Chao Yang, Juntao Li, Kangguo Cheng | 2022-05-03 |
| 11251288 | Nanosheet transistor with asymmetric gate stack | Ruilong Xie, Kangguo Cheng, Juntao Li, Dechao Guo, Tao Li +1 more | 2022-02-15 |
| 11176043 | Distributed memory-augmented neural network architecture | Ahmet S. Ozcan, Tomasz Kornuta, Nicolas Antoine | 2021-11-16 |
| 11175844 | Optimal placement of data structures in a hybrid memory based inference computing platform | Ashish Ranjan, Arvind Kumar | 2021-11-16 |
| 11152307 | Buried local interconnect | Kangguo Cheng, Lawrence A. Clevenger, Junli Wang, John H. Zhang | 2021-10-19 |
| 11107731 | Self-aligned repaired top via | Ruilong Xie, Chih-Chao Yang, Juntao Li, Kangguo Cheng | 2021-08-31 |
| 11081172 | On-chip security key with phase change memory | Kangguo Cheng, Ruilong Xie, Juntao Li | 2021-08-03 |
| 11038106 | Phase change memory cell with a metal layer | Kangguo Cheng, Juntao Li, Ruilong Xie | 2021-06-15 |
| 11024551 | Metal replacement vertical interconnections for buried capacitance | Hsueh-Chung Chen, Lawrence A. Clevenger, Daniel James Dechene, Somnath Ghosh | 2021-06-01 |
| 10985063 | Semiconductor device with local connection | Kangguo Cheng, Lawrence A. Clevenger, Junli Wang, John H. Zhang | 2021-04-20 |
| 10950722 | Vertical gate all-around transistor | John H. Zhang, Lawrence A. Clevenger, Yiheng Xu | 2021-03-16 |
| 10930553 | Forming self-aligned vias and air-gaps in semiconductor fabrication | Lawrence A. Clevenger, John H. Zhang | 2021-02-23 |
| 10833204 | Multiple width nanosheet devices | Kangguo Cheng, Lawrence A. Clevenger, Junli Wang, John H. Zhang | 2020-11-10 |
| 10832916 | Self-aligned gate isolation with asymmetric cut placement | Ruilong Xie, Kangguo Cheng, Veeraraghavan S. Basker | 2020-11-10 |