Issued Patents All Time
Showing 76–100 of 408 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10008500 | Semiconductor devices | Kangguo Cheng | 2018-06-26 |
| 10002876 | FinFET vertical flash memory | Ramachandra Divakaruni, Arvind Kumar | 2018-06-19 |
| 9911652 | Forming self-aligned vias and air-gaps in semiconductor fabrication | Lawrence A. Clevenger, John H. Zhang | 2018-03-06 |
| 9905511 | Modular fuses and antifuses for integrated circuits | John H. Zhang, Yiheng Xu, Lawrence A. Clevenger, Edem Wornyo | 2018-02-27 |
| 9837394 | Self-aligned three dimensional chip stack and method for making the same | Lawrence A. Clevenger, Yiheng Xu, John H. Zhang | 2017-12-05 |
| 9786551 | Trench structure for high performance interconnection lines of different resistivity and method of making same | John H. Zhang, Lawrence A. Clevenger, Yiheng Xu, Richard S. Wise | 2017-10-10 |
| 9755030 | Method for reduced source and drain contact to gate stack capacitance | Richard Q. Williams | 2017-09-05 |
| 9741613 | Method for producing self-aligned line end vias and related device | John H. Zhang, Lawrence A. Clevenger | 2017-08-22 |
| 9660105 | Finfet crosspoint flash memory | Ramachandra Divakaruni, Arvind Kumar | 2017-05-23 |
| 9659820 | Interconnect structure having large self-aligned vias | John H. Zhang, Lawrence A. Clevenger, Yiheng Xu, Richard S. Wise, Akil Khamisi Sutton +2 more | 2017-05-23 |
| 9659818 | Forming self-aligned dual patterning mandrel and non-mandrel interconnects | Lawrence A. Clevenger, John H. Zhang | 2017-05-23 |
| 9658523 | Interconnect structure having large self-aligned vias | John H. Zhang, Lawrence A. Clevenger, Yiheng Xu, Richard S. Wise, Terry A. Spooner +1 more | 2017-05-23 |
| 9646939 | Multilayer structure in an integrated circuit for damage prevention and detection and methods of creating the same | John H. Zhang, Lawrence A. Clevenger, Yiheng Xu, Byoung Youp Kim, Walter Kleemeier | 2017-05-09 |
| 9640765 | Carbon nanotube device | Lawrence A. Clevenger, Chandrasekhar Narayan, Gregory A. Northrop, Brian C. Sapp | 2017-05-02 |
| 9640552 | Multi-height fin field effect transistors | Pranita Kerber, Sudesh Saroop | 2017-05-02 |
| 9633986 | Technique for fabrication of microelectronic capacitors and resistors | John H. Zhang, Lawrence A. Clevenger, Yiheng Xu, Edem Wornyo | 2017-04-25 |
| 9607893 | Method of forming self-aligned metal lines and vias | John H. Zhang, Lawrence A. Clevenger | 2017-03-28 |
| 9601570 | Structure for reduced source and drain contact to gate stack capacitance | Richard Q. Williams | 2017-03-21 |
| 9530866 | Methods of forming vertical transistor devices with self-aligned top source/drain conductive contacts | John H. Zhang, Steven Bentley, Brian Alexander Cohen, Kwan-Yong Lim | 2016-12-27 |
| 9530863 | Methods of forming vertical transistor devices with self-aligned replacement gate structures | John H. Zhang, Steven Bentley, Brian Alexander Cohen, Kwan-Yong Lim | 2016-12-27 |
| 9511918 | Self-locking container | Ira L. Allen, Lawrence A. Clevenger, Kevin S. Petrarca | 2016-12-06 |
| 9496415 | Structure and process for overturned thin film device with self-aligned gate and S/D contacts | Lawrence A. Clevenger, Yiheng Xu, John H. Zhang | 2016-11-15 |
| 9472558 | Semiconductor structures with stacked non-planar field effect transistors and methods of forming the structures | Kangguo Cheng, Ali Khakifirooz, Robert C. Wong | 2016-10-18 |
| 9472402 | Methods and structures for protecting one area while processing another area on a chip | Deok-kee Kim, Kenneth T. Settlemyer, Jr., Kangguo Cheng, Ramachandra Divakaruni, Dirk Pfeiffer +4 more | 2016-10-18 |
| 9431523 | Local thinning of semiconductor fins | Kangguo Cheng, Ramachandra Divakaruni | 2016-08-30 |