Issued Patents All Time
Showing 76–100 of 160 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10090240 | Interconnect structure with capacitor element and related methods | Chih-Chao Yang, Keith Kwong Hon Wong | 2018-10-02 |
| 10083862 | Protective liner between a gate dielectric and a gate contact | Lawrence A. Clevenger, Kirk D. Peterson, Junli Wang | 2018-09-25 |
| 10062647 | Interconnect structure having tungsten contact copper wiring | Anthony K. Stamper | 2018-08-28 |
| 10020256 | Electronic fuse having an insulation layer | Chad M. Burke, Keith Kwong Hon Wong, Chih-Chao Yang | 2018-07-10 |
| 10014255 | Contacts having a geometry to reduce resistance | Lawrence A. Clevenger, Kirk D. Peterson, Terry A. Spooner, Junli Wang | 2018-07-03 |
| 9997408 | Method of optimizing wire RC for device performance and reliability | Lawrence A. Clevenger, Kirk D. Peterson, John E. Sheets, II, Terry A. Spooner | 2018-06-12 |
| 9966308 | Semiconductor device and method of forming the semiconductor device | Lawrence A. Clevenger, Kirk D. Peterson, John E. Sheets, II, Junli Wang, Chih-Chao Yang | 2018-05-08 |
| 9940430 | Burn-in power performance optimization | Jeanne P. Bickford, Nazmul Habib, Tad J. Wilder | 2018-04-10 |
| 9891275 | Integrated circuit chip reliability qualification using a sample-specific expected fail rate | Jeanne P. Bickford, Nazmul Habib, Tad J. Wilder | 2018-02-13 |
| 9880892 | System and method for managing semiconductor manufacturing defects | Jeanne P. Bickford, Nazmul Habib, Pascal A. Nsame | 2018-01-30 |
| 9837309 | Semiconductor via structure with lower electrical resistance | Lawrence A. Clevenger, Kirk D. Peterson, Terry A. Spooner, Junli Wang | 2017-12-05 |
| 9791502 | On-chip usable life depletion meter and associated method | Jeanne P. Bickford, Nazmul Habib, Tad J. Wilder | 2017-10-17 |
| 9768116 | Optimized wires for resistance or electromigration | Lawrence A. Clevenger, Kirk D. Peterson | 2017-09-19 |
| 9759766 | Electromigration test structure for Cu barrier integrity and blech effect evaluations | Griselda Bonilla, Elbert E. Huang, Chao-Kun Hu, Paul S. McLaughlin | 2017-09-12 |
| 9761482 | Enhancement of iso-via reliability | Lawrence A. Clevenger, Xiao Hu Liu, Kirk D. Peterson | 2017-09-12 |
| 9761526 | Interconnect structure having tungsten contact copper wiring | Anthony K. Stamper | 2017-09-12 |
| 9711452 | Optimized wires for resistance or electromigration | Lawrence A. Clevenger, Kirk D. Peterson | 2017-07-18 |
| 9685407 | Optimized wires for resistance or electromigration | Lawrence A. Clevenger, Kirk D. Peterson | 2017-06-20 |
| 9659817 | Structure and process for W contacts | Daniel C. Edelstein, Chih-Chao Yang | 2017-05-23 |
| 9653403 | Structure and process for W contacts | Daniel C. Edelstein, Chih-Chao Yang | 2017-05-16 |
| 9639645 | Integrated circuit chip reliability using reliability-optimized failure mechanism targeting | Jeanne P. Bickford, Nazmul Habib, Tad J. Wilder | 2017-05-02 |
| 9625325 | System and method for identifying operating temperatures and modifying of integrated circuits | Jeanne P. Bickford, Nazmul Habib, Tad J. Wilder | 2017-04-18 |
| 9618566 | Systems and methods to prevent incorporation of a used integrated circuit chip into a product | Jeanne P. Bickford, Nazmul Habib, Tad J. Wilder | 2017-04-11 |
| 9576880 | Dual damascene structure with liner | Chih-Chao Yang | 2017-02-21 |
| 9570389 | Interconnect structure | Dinesh A. Badami, Wen Liu, Chih-Chao Yang | 2017-02-14 |