Issued Patents All Time
Showing 101–125 of 160 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9548270 | Electrical fuse with metal line migration | Yan Li, Keith Kwong Hon Wong, Chih-Chao Yang | 2017-01-17 |
| 9514981 | Interconnect structure | Dinesh A. Badami, Wen Liu, Chih-Chao Yang | 2016-12-06 |
| 9489482 | Reliability-optimized selective voltage binning | Jeanne P. Bickford, Nazmul Habib, Tad J. Wilder | 2016-11-08 |
| 9472477 | Electromigration test structure for Cu barrier integrity and blech effect evaluations | Griselda Bonilla, Elbert E. Huang, Chao-Kun Hu, Paul S. McLaughlin | 2016-10-18 |
| 9406617 | Structure and process for W contacts | Daniel C. Edelstein, Chih-Chao Yang | 2016-08-02 |
| 9362229 | Semiconductor devices with enhanced electromigration performance | Jeffrey P. Gambino, David L. Harame, Timothy D. Sullivan, Bjorn K. A. Zetterlund | 2016-06-07 |
| 9354953 | System integrator and system integration method with reliability optimized integrated circuit chip selection | Jeanne P. Bickford, Nazmul Habib | 2016-05-31 |
| 9312203 | Dual damascene structure with liner | Chih-Chao Yang | 2016-04-12 |
| 9287185 | Determining appropriateness of sampling integrated circuit test data in the presence of manufacturing variations | Griselda Bonilla, Barry P. Linder, James H. Stathis, Ernest Y. Wu, Kai Zhao | 2016-03-15 |
| 9224640 | Method to improve fine Cu line reliability in an integrated circuit device | Chad M. Burke, Keith Kwong Hon Wong, Chih-Chao Yang | 2015-12-29 |
| 9159653 | Copper interconnect structures and methods of making same | Chih-Chao Yang, Marc A. Bergendahl, David V. Horak, Shom Ponoth | 2015-10-13 |
| 9129964 | Programmable electrical fuse | Jason Coyner, Keith Kwong Hon Wong, Chih-Chao Yang | 2015-09-08 |
| 9064087 | Semiconductor device reliability model and methodologies for use thereof | Jeanne P. Bickford, Nazmul Habib, Pascal A. Nsame | 2015-06-23 |
| 9058250 | In-situ computing system failure avoidance | Jeanne P. Bickford, Nazmul Habib, Pascal A. Nsame | 2015-06-16 |
| 9026981 | Dielectric reliability assessment for advanced semiconductors | James H. Stathis, Ernest Y. Wu | 2015-05-05 |
| 8999767 | Electronic fuse having an insulation layer | Chad M. Burke, Keith Kwong Hon Wong, Chih-Chao Yang | 2015-04-07 |
| 8952486 | Electrical fuse and method of making the same | Chih-Chao Yang, Stephen M. Gates, Dan Edelstein | 2015-02-10 |
| 8943444 | Semiconductor device reliability model and methodologies for use thereof | Jeanne P. Bickford, Nazmul Habib, Pascal A. Nsame | 2015-01-27 |
| 8922022 | Electromigration resistant via-to-line interconnect | Paul S. McLaughlin, Timothy D. Sullivan | 2014-12-30 |
| 8901738 | Method of manufacturing an enhanced electromigration performance hetero-junction bipolar transistor | Jeffrey P. Gambino, David L. Harame, Timothy D. Sullivan, Bjorn K. A. Zetterlund | 2014-12-02 |
| 8896090 | Electrical fuses and methods of making electrical fuses | Nicholas R. Hogle, Keith Kwong Hon Wong, Chih-Chao Yang | 2014-11-25 |
| 8839180 | Dielectric reliability assessment for advanced semiconductors | James H. Stathis, Ernest Y. Wu | 2014-09-16 |
| 8802559 | Interconnect structure with an electromigration and stress migration enhancement liner | Chih-Chao Yang | 2014-08-12 |
| 8802558 | Copper interconnect structures and methods of making same | Chih-Chao Yang, Marc A. Bergendahl, David V. Horak, Shom Ponoth | 2014-08-12 |
| 8779491 | 3D via capacitor with a floating conductive plate for improved reliability | Chih-Chao Yang, Fen Chen | 2014-07-15 |