Issued Patents All Time
Showing 151–175 of 235 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9425079 | Semiconductor structure with integrated passive structures | Anthony I. Chou, Renee T. Mo, Shreesh Narasimha | 2016-08-23 |
| 9418903 | Structure and method for effective device width adjustment in finFET devices using gate workfunction shift | Ramachandra Divakaruni, Carl Radens | 2016-08-16 |
| 9412667 | Asymmetric high-k dielectric for reducing gate induced drain leakage | Anthony I. Chou, Chung-Hsun Lin, Shreesh Narasimha, Claude Ortolland, Jonathan T. Shaw | 2016-08-09 |
| 9412759 | CMOS gate contact resistance reduction | Anthony I. Chou, Sungjae Lee | 2016-08-09 |
| 9401325 | Planar polysilicon regions for precision resistors and electrical fuses and method of fabrication | Anthony I. Chou, Renee T. Mo, Shreesh Narasimha | 2016-07-26 |
| 9400511 | Methods and control systems of resistance adjustment of resistors | Anthony I. Chou, Sungjae Lee | 2016-07-26 |
| 9379185 | Method of forming channel region dopant control in fin field effect transistor | Murshed Chowdhury, Brian J. Greene | 2016-06-28 |
| 9378171 | High performance interconnect physical layer | Venkatraman Iyer, Darren S. Jue, Rahul C. Shah | 2016-06-28 |
| 9311512 | Apparatus and method to harden computer system | Naga Gurumoorthy, Matthew J. Parker | 2016-04-12 |
| 9305930 | Finfet crosspoint flash memory | Ramachandra Divakaruni, Carl Radens | 2016-04-05 |
| 9299780 | Constrained epitaxial source/drain regions on semiconductor-on-insulator finFET device | Brian J. Greene, Dan M. Mocuta | 2016-03-29 |
| 9287399 | Faceted intrinsic epitaxial buffer layer for reducing short channel effects while maximizing channel stress levels | Bhupesh Chandra, Paul Chang, Gregory G. Freeman, Dechao Guo, Judson R. Holt +6 more | 2016-03-15 |
| 9269786 | Silicon nitride layer deposited at low temperature to prevent gate dielectric regrowth high-K metal gate field effect transistors | Anthony I. Chou, Shreesh Narasimha, Claude Ortolland, Kai Zhao | 2016-02-23 |
| 9268594 | Processor extensions for execution of secure embedded containers | Vedvyas Shanbhogue, Purushottam Goel | 2016-02-23 |
| 9252215 | Constrained epitaxial source/drain regions on semiconductor-on-insulator finFET device | Brian J. Greene, Dan M. Mocuta | 2016-02-02 |
| 9240431 | Conductive trench isolation | Yuanwei Zheng, Gang Chen, Duli Mao, Dyson H. Tai, Chih-Wei Hsiung | 2016-01-19 |
| 9219059 | Semiconductor structure with integrated passive structures | Anthony I. Chou, Renee T. Mo, Shreesh Narasimha | 2015-12-22 |
| 9195824 | Providing integrity verification and attestation in a hidden execution environment | Ned M. Smith, Vedvyas Shanbhogue, Purushottam Goel | 2015-11-24 |
| 9190313 | Shallow trench isolation structures | Bruce B. Doris, Kangguo Cheng, Balasubramanian S. Haran, Ali Khakifirooz, Pranita Kerber +1 more | 2015-11-17 |
| 9190418 | Junction butting in SOI transistor with embedded source/drain | Anthony I. Chou, Murshed Chowdhury, Robert R. Robison | 2015-11-17 |
| 9111993 | Conductive trench isolation | Yuanwei Zheng, Gang Chen, Duli Mao, Dyson H. Tai, Chih-Wei Hsiung | 2015-08-18 |
| 9104793 | Method and system of adapting communication links to link conditions on a platform | Venkatraman Iyer, Santanu Chaudhuri, Darren S. Jue, Dennis R. Halicki | 2015-08-11 |
| 9086913 | Processor extensions for execution of secure embedded containers | Vedvyas Shanbhogue, Purushottam Goel | 2015-07-21 |
| 9064972 | Method of forming a gated diode structure for eliminating RIE damage from cap removal | Anthony I. Chou, Edward P. Maciejewski, Shreesh Narasimha, Dustin K. Slisher | 2015-06-23 |
| 9059243 | Shallow trench isolation structures | Bruce B. Doris, Kangguo Cheng, Balasubramanian S. Haran, Ali Khakifirooz, Pranita Kulkarni +1 more | 2015-06-16 |