Issued Patents All Time
Showing 101–125 of 235 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10032862 | Semiconductor structure with integrated passive structures | Anthony I. Chou, Renee T. Mo, Shreesh Narasimha | 2018-07-24 |
| 10025981 | Visual object and event detection and prediction system using saccades | Ban Kawas, Janusz Marecki, Sharathchandra U. Pankanti | 2018-07-17 |
| D822658 | Computer notebook | Jim Okuley, Murali Veeramoney, Prosenjit Ghosh, Denica N. Larsen, Martin Bone +2 more | 2018-07-10 |
| 10002876 | FinFET vertical flash memory | Ramachandra Divakaruni, Carl Radens | 2018-06-19 |
| 10002900 | Three-dimensional wafer scale integration of heterogeneous wafers with unequal die sizes | Mark C. H. Lamorey | 2018-06-19 |
| 9991167 | Method and IC structure for increasing pitch between gates | Murshed Chowdhury, Brian J. Greene, Chung-Hsun Lin | 2018-06-05 |
| 9934138 | Application testing on a blockchain | Vijay Kumar Ananthapur Bache, Jhilam Bera, Bidhu Ranjan Sahoo | 2018-04-03 |
| 9922831 | Asymmetric high-k dielectric for reducing gate induced drain leakage | Anthony I. Chou, Chung-Hsun Lin, Shreesh Narasimha, Claude Ortolland, Jonathan T. Shaw | 2018-03-20 |
| 9923082 | Junction butting structure using nonuniform trench shape | Anthony I. Chou, Judson R. Holt, Henry K. Utomo | 2018-03-20 |
| 9904341 | Cascading power consumption | Brian E. Woodruff, David M. Putzolu, Mark R. Walker | 2018-02-27 |
| 9892086 | High performance interconnect physical layer | Venkatraman Iyer, Darren S. Jue, Rahul C. Shah | 2018-02-13 |
| 9886193 | Architecture and implementation of cortical system, and fabricating an architecture using 3D wafer scale integration | Daniel G. Berger, Troy L. Graves-Abe, Subramanian S. Iyer, Toshiaki Kirihata, Winfried W. Wilcke | 2018-02-06 |
| 9881956 | Heterogeneous integration using wafer-to-wafer stacking with die size adjustment | Mark C. H. Lamorey | 2018-01-30 |
| 9870503 | Visual object and event detection and prediction system using saccades | Ban Kawas, Janusz Marecki, Sharathchandra U. Pankanti | 2018-01-16 |
| 9859122 | Asymmetric high-k dielectric for reducing gate induced drain leakage | Anthony I. Chou, Chung-Hsun Lin, Shreesh Narasimha, Claude Ortolland, Jonathan T. Shaw | 2018-01-02 |
| 9837319 | Asymmetric high-K dielectric for reducing gate induced drain leakage | Anthony I. Chou, Chung-Hsun Lin, Shreesh Narasimha, Claude Ortolland, Jonathan T. Shaw | 2017-12-05 |
| 9817054 | Electrical margining of multi-parameter high-speed interconnect links with multi-sample probing | Thanunathan Rangarajan, Shreesh Chhabbi, Venkatraman Iyer | 2017-11-14 |
| 9768071 | Asymmetric high-K dielectric for reducing gate induced drain leakage | Anthony I. Chou, Chung-Hsun Lin, Shreesh Narasimha, Claude Ortolland, Jonathan T. Shaw | 2017-09-19 |
| 9768195 | Semiconductor structure with integrated passive structures | Anthony I. Chou, Renee T. Mo, Shreesh Narasimha | 2017-09-19 |
| 9753557 | Fast inking a touch display | Ajay V. Bhatt, Balaji Vembu, Murali Ramadoss, Antonio S. Cheng, John J. Valavi +1 more | 2017-09-05 |
| 9721843 | Asymmetric high-k dielectric for reducing gate induced drain leakage | Anthony I. Chou, Chung-Hsun Lin, Shreesh Narasimha, Claude Ortolland, Jonathan T. Shaw | 2017-08-01 |
| 9703301 | Methods and control systems of resistance adjustment of resistors | Anthony I. Chou, Sungjae Lee | 2017-07-11 |
| 9698159 | Semiconductor structure with integrated passive structures | Anthony I. Chou, Renee T. Mo, Shreesh Narasimha | 2017-07-04 |
| 9691810 | Curved image sensor | Yuanwei Zheng, Gang Chen, Duli Mao, Dyson H. Tai, Hung-Chih Chang +1 more | 2017-06-27 |
| 9685379 | Asymmetric high-k dielectric for reducing gate induced drain leakage | Anthony I. Chou, Chung-Hsun Lin, Shreesh Narasimha, Claude Ortolland, Jonathan T. Shaw | 2017-06-20 |