Issued Patents All Time
Showing 51–71 of 71 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7875528 | Method, system, program product for bonding two circuitry-including substrates and related stage | Douglas C. La Tulipe, Jr., Steven E. Steen | 2011-01-25 |
| 7855101 | Layer transfer process and functionally enhanced integrated circuits produced thereby | Bruce K. Furman, Sampath Purushothaman, Muthumanickam Sankarapandian | 2010-12-21 |
| 7851357 | Method of forming electrodeposited contacts | Cyril Cabral, Jr., Lili Deligianni, Randolph F. Knarr, Sandra G. Malhotra, Stephen M. Rossnagel +2 more | 2010-12-14 |
| 7847357 | High performance CMOS devices comprising gapped dual stressors with dielectric gap fillers, and methods of fabricating the same | Bruce B. Doris, Thomas W. Dyer, David R. Medeiros | 2010-12-07 |
| 7786596 | Hermetic seal and reliable bonding structures for 3D applications | Kuan-Neng Chen, Bruce K. Furman, Edmund J. Sprogis, Cornelia K. Tsang, Matthew R. Wordeman +1 more | 2010-08-31 |
| 7696057 | Method for co-alignment of mixed optical and electron beam lithographic fabrication levels | David M. Fried, John Michael Hergenrother, Sharee McNab, Michael J. Rooks | 2010-04-13 |
| 7683478 | Hermetic seal and reliable bonding structures for 3D applications | Kuan-Neng Chen, Bruce K. Furman, Edmund J. Sprogis, Cornelia K. Tsang, Matthew R. Wordeman +1 more | 2010-03-23 |
| 7679164 | Bipolar transistor with silicided sub-collector | Francois Pagette, Christian Lavoie | 2010-03-16 |
| 7666723 | Methods of forming wiring to transistor and related transistor | David J. Frank, Douglas C. La Tulipe, Jr., Steven E. Steen | 2010-02-23 |
| 7611953 | Bipolar transistor with isolation and direct contacts | David C. Ahlgren, Gregory G. Freeman, Francois Pagette, Christopher M. Schnabel | 2009-11-03 |
| 7598540 | High performance CMOS devices comprising gapped dual stressors with dielectric gap fillers, and methods of fabricating the same | Bruce B. Doris, Thomas W. Dyer, David R. Medeiros | 2009-10-06 |
| 7585740 | Fully silicided extrinsic base transistor | David C. Ahlgren, Guy M. Cohen, Christian Lavoie, Francois Pagette | 2009-09-08 |
| 7550361 | Trench structure and method for co-alignment of mixed optical and electron beam lithographic fabrication levels | David M. Fried, John Michael Hergenrother, Sharee McNab, Michael J. Rooks | 2009-06-23 |
| 7528056 | Low-cost strained SOI substrate for high-performance CMOS technology | Meikei Ieong, Douglas C. La Tulipe, Jr., Leathen Shi, James Vichiconti, Albert M. Young | 2009-05-05 |
| 7498256 | Copper contact via structure using hybrid barrier layer | Randolph F. Knarr, Christopher D. Sheraw, Andrew H. Simon, Yun-Yu Wang, Keith Kwong Hon Wong | 2009-03-03 |
| 7488630 | Method for preparing 2-dimensional semiconductor devices for integration in a third dimension | David J. Frank, Douglas C. La Tulipe, Jr., Leathen Shi, Steven E. Steen | 2009-02-10 |
| 7405154 | Structure and method of forming electrodeposited contacts | Cyril Cabral, Jr., Hariklia Deligianni, Randolph F. Knarr, Sandra G. Malhotra, Stephen M. Rossnagel +2 more | 2008-07-29 |
| 7394113 | Self-alignment scheme for a heterojunction bipolar transistor | Francois Pagette | 2008-07-01 |
| 7217988 | Bipolar transistor with isolation and direct contacts | David C. Ahlgren, Gregory G. Freeman, Francois Pagette, Christopher M. Schnabel | 2007-05-15 |
| 7030481 | High density chip carrier with integrated passive devices | Michael P. Chudzik, Robert H. Dennard, Rama Divakaruni, Bruce K. Furman, Rajarao Jammy +3 more | 2006-04-18 |
| 6962872 | High density chip carrier with integrated passive devices | Michael P. Chudzik, Robert H. Dennard, Rama Divakaruni, Bruce K. Furman, Rajarao Jammy +3 more | 2005-11-08 |