Issued Patents All Time
Showing 251–275 of 767 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9515173 | Method of fabricating electrostatically enhanced fins and stacked nanowire field effect transistors | Kangguo Cheng, Pouya Hashemi, Ali Khakifirooz, Alexander Reznicek | 2016-12-06 |
| 9515185 | Silicon germanium-on-insulator FinFET | Qing Liu, Hong He | 2016-12-06 |
| 9508829 | Nanosheet MOSFET with full-height air-gap spacer | Kangguo Cheng, Michael A. Guillorn, Xin Miao | 2016-11-29 |
| 9508851 | Formation of bulk SiGe fin with dielectric isolation by anodization | Thomas N. Adam, Kangguo Cheng, Pouya Hashemi, Ali Khakifirooz, Alexander Reznicek | 2016-11-29 |
| 9508741 | CMOS structure on SSOI wafer | Hong He, Ali Khakifirooz, Junli Wang | 2016-11-29 |
| 9502540 | Uniform height tall fins with varying silicon germanium concentrations | Stephen W. Bedell, Keith E. Fogel, Alexander Reznicek | 2016-11-22 |
| 9502243 | Multi-orientation SOI substrates for co-integration of different conductivity type semiconductor devices | Kangguo Cheng, Pouya Hashemi, Ali Khakifirooz, Alexander Reznicek | 2016-11-22 |
| 9502292 | Dual shallow trench isolation liner for preventing electrical shorts | Shom Ponoth, Prasanna Khare, Qing Liu, Nicolas Loubet, Maud Vinet | 2016-11-22 |
| 9502411 | Strained finFET device fabrication | Hong He, Sivananda K. Kanakasabapathy, Gauri Karve, Fee Li Lie, Stuart A. Sieg | 2016-11-22 |
| 9496186 | Uniform height tall fins with varying silicon germanium concentrations | Stephen W. Bedell, Keith E. Fogel, Alexander Reznicek | 2016-11-15 |
| 9496343 | Secondary use of aspect ratio trapping holes as eDRAM structure | Kangguo Cheng, Ali Khakifirooz, Alexander Reznicek | 2016-11-15 |
| 9496281 | Dual isolation on SSOI wafer | Hong He, Ali Khakifirooz, Junli Wang | 2016-11-15 |
| 9490161 | Channel SiGe devices with multiple threshold voltages on hybrid oriented substrates, and methods of manufacturing same | Lisa F. Edge, Pouya Hashemi, Alexander Reznicek | 2016-11-08 |
| 9490335 | Extra gate device for nanosheet | Terence B. Hook, Junli Wang | 2016-11-08 |
| 9484359 | MOSFET with work function adjusted metal backgate | Kangguo Cheng, Pranita Kerber, Ali Khakifirooz | 2016-11-01 |
| 9478658 | Device and method for fabricating thin semiconductor channel and buried strain memorization layer | Kangguo Cheng, Ali Khakifirooz, Pranita Kulkarni, Ghavam G. Shahidi | 2016-10-25 |
| 9472616 | Undercut insulating regions for silicon-on-insulator device | Kangguo Cheng, Balasubramanian Pranatharthiharan, Shom Ponoth, Theodorus E. Standaert, Tenko Yamashita | 2016-10-18 |
| 9472621 | CMOS structures with selective tensile strained NFET fins and relaxed PFET fins | Hong He, Ali Khakifirooz, Joshua M. Rubin | 2016-10-18 |
| 9466567 | Nanowire compatible E-fuse | Kangguo Cheng, Pouya Hashemi, Ali Khakifirooz, Alexander Reznicek | 2016-10-11 |
| 9461169 | Device and method for fabricating thin semiconductor channel and buried strain memorization layer | Kangguo Cheng, Ali Khakifirooz, Pranita Kulkarni, Ghavam G. Shahidi | 2016-10-04 |
| 9455274 | Replacement fin process in SSOI wafer | Hong He, Ali Khakifirooz, Junli Wang | 2016-09-27 |
| 9455336 | SiGe and Si FinFET structures and methods for making the same | Kangguo Cheng, Pouya Hashemi, Ali Khakifirooz, Alexander Reznicek | 2016-09-27 |
| 9443948 | Gate-all-around nanowire MOSFET and method of formation | Kangguo Cheng, Pouya Hashemi, Ali Khakifirooz, Alexander Reznicek | 2016-09-13 |
| 9437675 | eDRAM for planar III-V semiconductor devices | Kangguo Cheng, Ali Khakifirooz, Alexander Reznicek | 2016-09-06 |
| 9437679 | Semi-conductor device with epitaxial source/drain facetting provided at the gate edge | Thomas N. Adam, Kangguo Cheng, Ali Khakifirooz, Alexander Reznicek | 2016-09-06 |