Issued Patents All Time
Showing 26–50 of 60 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7019366 | Electrostatic discharge performance of a silicon structure and efficient use of area with electrostatic discharge protective device under the pad approach and adjustment of via configuration thereto to control drain junction resistance | Nian Yang, Hiroyuki Ogawa, Kuo-Tung Chang, Yu Sun | 2006-03-28 |
| 6963104 | Non-volatile memory device | Bin Yu | 2005-11-08 |
| 6958512 | Non-volatile memory device | Shibly S. Ahmed, Haihong Wang, Bin Yu | 2005-10-25 |
| 6933558 | Flash memory device | Wiley Eugene Hill, Haihong Wang, Bin Yu | 2005-08-23 |
| 6919247 | Method of fabricating a floating gate | Kuo-Tung Chang | 2005-07-19 |
| 6897533 | Multi-bit silicon nitride charge-trapping non-volatile memory cell | Jean Y. Yang | 2005-05-24 |
| 6869844 | Method and structure for protecting NROM devices from induced charge damage during device fabrication | Zhizheng Liu, Jean Y. Yang | 2005-03-22 |
| 6797565 | Methods for fabricating and planarizing dual poly scalable SONOS flash memory | Jean Y. Yang, Zhizheng Liu | 2004-09-28 |
| 6767791 | Structure and method for suppressing oxide encroachment in a floating gate memory cell | Harpreet Sachar, Jean Y. Yang | 2004-07-27 |
| 6754106 | Reference cell with various load circuits compensating for source side loading effects in a non-volatile memory | Jean Y. Yang, Jiang Li | 2004-06-22 |
| 6737701 | Structure and method for reducing charge loss in a memory cell | Amy C. Tu, Jean Y. Yang | 2004-05-18 |
| 6707078 | Dummy wordline for erase and bitline leakage | Hidehiko Shiraiwa, Jean Y. Yang, Mark T. Ramsbey, Darlene Hamilton | 2004-03-16 |
| 6706595 | Hard mask process for memory device without bitline shorts | Jean Y. Yang, Mark T. Ramsbey, Hidehiko Shiraiwa, Emmanuil Lingunis, Tazrien Kamal | 2004-03-16 |
| 6680509 | Nitride barrier layer for protection of ONO structure from top oxide loss in fabrication of SONOS flash memory | Jean Y. Yang, Mark T. Ramsbey, Emmanuel H. Lingunis, Yu Sun | 2004-01-20 |
| 6667243 | Etch damage repair with thermal annealing | Mark T. Ramsbey, Nicholas H. Tripsas, Arvind Halliyal, Jeffrey A. Shields | 2003-12-23 |
| 6664191 | Non self-aligned shallow trench isolation process with disposable space to define sub-lithographic poly space | Unsoon Kim, Yu Sun, Michael K. Templeton, Angela T. Hui, Chi Chang | 2003-12-16 |
| 6628545 | Memory circuit for suppressing bit line current leakage | Jiang Li, Zhizheng Liu | 2003-09-30 |
| 6607925 | Hard mask removal process including isolation dielectric refill | Unsoon Kim, Dawn Hopper, Krishnashree Achuthan | 2003-08-19 |
| 6566736 | Die seal for semiconductor device moisture protection | Hiroyuki Ogawa, Yu Sun | 2003-05-20 |
| 6555436 | Simultaneous formation of charge storage and bitline to wordline isolation | Mark T. Ramsbey, Jean Y. Yang, Hidehiko Shiraiwa, Michael A. Van Buskirk, David Michael Rogers +3 more | 2003-04-29 |
| 6512701 | Erase method for dual bit virtual ground flash | Darlene Hamilton, Kulachet Tanpairoj | 2003-01-28 |
| 6509232 | Formation of STI (shallow trench isolation) structures within core and periphery areas of flash memory device | Unsoon Kim, Mark S. Chang, Chi Chang, Angela T. Hui, Yu Sun | 2003-01-21 |
| 6468865 | Method of simultaneous formation of bitline isolation and periphery oxide | Jean Y. Yang, Mark T. Ramsbey, Hidehiko Shiraiwa, Michael A. Van Buskirk, David Michael Rogers +3 more | 2002-10-22 |
| 6465306 | Simultaneous formation of charge storage and bitline to wordline isolation | Mark T. Ramsbey, Jean Y. Yang, Hidehiko Shiraiwa, Michael A. Van Buskirk, David Michael Rogers +3 more | 2002-10-15 |
| 6445030 | Flash memory erase speed by fluorine implant or fluorination | Jean Y. Yang, Hidehiko Shiraiwa, Che-Hoo Ng | 2002-09-03 |