Issued Patents All Time
Showing 26–50 of 63 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10629512 | Integrated circuit die with in-chip heat sink | Hong-Tsz Pan, Jonathan Chang, Nui Chong, Henley Liu, Gamal Refai-Ahmed | 2020-04-21 |
| 10593638 | Methods of interconnect for high density 2.5D and 3D integration | Jaspreet S. Gandhi, Henley Liu | 2020-03-17 |
| 10527670 | Testing system for lid-less integrated circuit packages | Gamal Refai-Ahmed, Ivor G. Barber, Jaspreet S. Gandhi, Tien-Yu Lee, Henley Liu +2 more | 2020-01-07 |
| 10529645 | Methods and apparatus for thermal interface material (TIM) bond line thickness (BLT) reduction and TIM adhesion enhancement for efficient thermal management | Jaspreet S. Gandhi, Henley Liu, Tien-Yu Lee, Gamal Refai-Ahmed, Myongseob Kim +2 more | 2020-01-07 |
| 10468351 | Multi-chip silicon substrate-less chip packaging | Woon-Seong Kwon | 2019-11-05 |
| 10319606 | Chip package assembly with enhanced interconnects and method for fabricating the same | Jaspreet S. Gandhi, Tien-Yu Lee, Henley Liu, Ivor G. Barber | 2019-06-11 |
| 10262920 | Stacked silicon package having a thermal capacitance element | Gamal Refai-Ahmed, Brian D. Philofsky, Anthony Torza | 2019-04-16 |
| 10147664 | Dynamic mounting thermal management for devices on board | Gamal Refai-Ahmed, Daniel Elftmann, Brian D. Philofsky, Anthony Torza | 2018-12-04 |
| 10096502 | Method and apparatus for assembling and testing a multi-integrated circuit package | Gamal Refai-Ahmed, Mohsen H. Mardi, Tien-Yu Lee, Ivor G. Barber, Cheang-Whang Chang +1 more | 2018-10-09 |
| 10043730 | Stacked silicon package assembly having an enhanced lid | Gamal Refai-Ahmed, Tien-Yu Lee, Ferdinand F. Fernandez, Ivor G. Barber, Inderjit Singh +1 more | 2018-08-07 |
| 10038259 | Low insertion loss package pin structure and method | Paul Ying-Fung Wu, Sarajuddin Niazi, Raymond E. Anderson | 2018-07-31 |
| 9831104 | Techniques for molded underfill for integrated circuit dies | Woon-Seong Kwon | 2017-11-28 |
| 9812374 | Thermal management device with textured surface for extended cooling limit | Gamal Refai-Ahmed, Brian D. Philofsky | 2017-11-07 |
| 9627329 | Interposer with edge reinforcement and method for manufacturing same | Woon-Seong Kwon | 2017-04-18 |
| 9508563 | Methods for flip chip stacking | Woon-Seong Kwon | 2016-11-29 |
| 9418966 | Semiconductor assembly having bridge module for die-to-die interconnection | Woon-Seong Kwon | 2016-08-16 |
| 9245865 | Integrated circuit package with multi-trench structure on flipped substrate contacting underfill | Woon-Seong Kwon | 2016-01-26 |
| 9236341 | Through-silicon vias with metal system fill | Dong Woo Kim, Myung June Lee | 2016-01-12 |
| 9224697 | Multi-die integrated circuits implemented using spacer dies | Woon-Seong Kwon | 2015-12-29 |
| 9147661 | Solder bump structure with enhanced high temperature aging reliability and method for manufacturing same | Woon-Seong Kwon | 2015-09-29 |
| 9006030 | Warpage management for fan-out mold packaged integrated circuit | Woon-Seong Kwon, Paul Ying-Fung Wu, Manoj Nachnani | 2015-04-14 |
| 8946884 | Substrate-less interposer technology for a stacked silicon interconnect technology (SSIT) product | Woon-Seong Kwon, Namhoon Kim, Joong-Ho Kim | 2015-02-03 |
| 8618648 | Methods for flip chip stacking | Woon-Seong Kwon | 2013-12-31 |
| RE44629 | Process for assembling an integrated circuit package having a substrate vent hole | Nagesh Vodrahalli, Michael J. Costello, Mun Leong Loke, Ravi Mahajan | 2013-12-10 |
| 7141448 | Controlled collapse chip connection (C4) integrated circuit package which has two dissimilar underfill materials | Venkatesan Murali, Duane Cook | 2006-11-28 |