Issued Patents All Time
Showing 176–200 of 608 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6214123 | Chemical vapor deposition systems and methods for depositing films on semiconductor wafers | Mark C. Gilmer, Robert Paiz | 2001-04-10 |
| 6211025 | Method of making elevated source/drain using poly underlayer | Mark C. Gilmer | 2001-04-03 |
| 6211000 | Method of making high performance mosfets having high conductivity gate conductors | Thomas E. Spikes, Jr., H. Jim Fulford | 2001-04-03 |
| 6210999 | Method and test structure for low-temperature integration of high dielectric constant gate dielectrics into self-aligned semiconductor devices | John L. Nistler, Charles E. May | 2001-04-03 |
| 6207995 | High K integration of gate dielectric with integrated spacer formation for high speed CMOS | Dim-Lee Kwong, H. Jim Fulford | 2001-03-27 |
| 6207544 | Method of fabricating ultra thin nitride spacers and device incorporating same | Thien T. Nguyen, Charles E. May | 2001-03-27 |
| 6207520 | Rapid thermal anneal with a gaseous dopant species for formation of lightly doped regions | H. Jim Fulford | 2001-03-27 |
| 6207485 | Integration of high K spacers for dual gate oxide channel fabrication technique | H. James Fulford, Charles E. May | 2001-03-27 |
| 6204153 | Argon doped epitaxial layers for inhibiting punchthrough within a semiconductor device | H. Jim Fulford, Charles E. May | 2001-03-20 |
| 6204148 | Method of making a semiconductor device having a grown polysilicon layer | H. Jim Fulford, Derick J. Wristers | 2001-03-20 |
| 6204130 | Semiconductor device having reduced polysilicon gate electrode width and method of manufacture thereof | Mark C. Gilmer | 2001-03-20 |
| 6201278 | Trench transistor with insulative spacers | Robert Dawson, H. Jim Fulford, Frederick N. Hause, Mark W. Michael, Bradley T. Moore +1 more | 2001-03-13 |
| 6200865 | Use of sacrificial dielectric structure to form semiconductor device with a self-aligned threshold adjust and overlying low-resistance gate | H. Jim Fulford | 2001-03-13 |
| 6200862 | Mask for asymmetrical transistor formation with paired transistors | Frederick N. Hause, Michael Duane | 2001-03-13 |
| 6197644 | High density mosfet fabrication method with integrated device scaling | Mark C. Gilmer | 2001-03-06 |
| 6197645 | Method of making an IGFET with elevated source/drain regions in close proximity to gate with sloped sidewalls | Mark W. Michael, Robert Dawson, H. Jim Fulford, Frederick N. Hause, Bradley T. Moore +1 more | 2001-03-06 |
| 6197668 | Ferroelectric-enhanced tantalum pentoxide for dielectric material applications in CMOS devices | Mark C. Gilmer | 2001-03-06 |
| 6197647 | Method of forming ultra-thin oxides with low temperature oxidation | Mark C. Gilmer | 2001-03-06 |
| 6194768 | High dielectric constant gate dielectric with an overlying tantalum gate conductor formed on a sidewall surface of a sacrificial structure | Frederick N. Hause, Charles E. May | 2001-02-27 |
| 6194283 | High density trench fill due to new spacer fill method including isotropically etching silicon nitride spacers | Robert Paiz, Thomas E. Spikes, Jr. | 2001-02-27 |
| 6191446 | Formation and control of a vertically oriented transistor channel length | John J. Bush, Jon D. Cheek | 2001-02-20 |
| 6188114 | Method of forming an insulated-gate field-effect transistor with metal spacers | Robert Dawson, H. Jim Fulford, Frederick N. Hause, Mark W. Michael, Bradley T. Moore +1 more | 2001-02-13 |
| 6188110 | Integration of isolation with epitaxial growth regions for enhanced device formation | H. Jim Fulford | 2001-02-13 |
| 6188107 | High performance transistor fabricated on a dielectric film and method of making same | Frederick N. Hause, Derick J. Wristers | 2001-02-13 |
| 6188106 | MOSFET having a highly doped channel liner and a dopant seal to provide enhanced device properties | H. Jim Fulford, Charles E. May | 2001-02-13 |