Issued Patents All Time
Showing 126–150 of 608 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6372588 | Method of making an IGFET using solid phase diffusion to dope the gate, source and drain | Derick J. Wristers, Robert Dawson, H. Jim Fulford, Frederick N. Hause, Mark W. Michael +1 more | 2002-04-16 |
| 6365943 | High density integrated circuit | Daniel Kadosh, Fred N. Hause | 2002-04-02 |
| 6362510 | Semiconductor topography having improved active device isolation and reduced dopant migration | H. Jim Fulford, Charles E. May | 2002-03-26 |
| 6358828 | Ultra high density series-connected transistors formed on separate elevational levels | Daniel Kadosh | 2002-03-19 |
| 6355955 | Transistor and a method for forming the transistor with elevated and/or relatively shallow source/drain regions to achieve enhanced gate electrode formation | H. Jim Fulford, Daniel Kadosh | 2002-03-12 |
| 6326251 | Method of making salicidation of source and drain regions with metal gate MOSFET | H. Jim Fulford, Thomas E. Spikes, Jr. | 2001-12-04 |
| 6323519 | Ultrathin, nitrogen-containing MOSFET sidewall spacers using low-temperature semiconductor fabrication process | Derick J. Wristers, Charles E. May | 2001-11-27 |
| 6323561 | Spacer formation for precise salicide formation | Fred N. Hause, Charles E. May | 2001-11-27 |
| 6309936 | Integrated formation of LDD and non-LDD semiconductor devices | Robert Paiz, Thomas E. Spikes, Jr. | 2001-10-30 |
| 6306763 | Enhanced salicidation technique | H. Jim Fulford | 2001-10-23 |
| 6303962 | Dielectrically-isolated transistor with low-resistance metal source and drain formed using sacrificial source and drain structures | H. Jim Fulford, Charles E. May | 2001-10-16 |
| 6300661 | Mutual implant region used for applying power/ground to a source of a transistor and a well of a substrate | Daniel Kadosh, Michael Duane | 2001-10-09 |
| 6297535 | Transistor having a gate dielectric which is substantially resistant to drain-side hot carrier injection | H. Jim Fulford | 2001-10-02 |
| 6288432 | Semiconductor fabrication employing a post-implant anneal within a low temperature, high pressure nitrogen ambient to improve channel and gate oxide reliability | Fred N. Hause | 2001-09-11 |
| 6281132 | Device and method for etching nitride spacers formed upon an integrated circuit gate conductor | Thien T. Nguyen, Charles E. May | 2001-08-28 |
| 6274442 | Transistor having a nitrogen incorporated epitaxially grown gate dielectric and method of making same | H. Jim Fulford, Charles E. May | 2001-08-14 |
| 6268634 | Transistor with an ultra short channel length defined by a laterally diffused nitrogen implant | H. Jim Eulford, Jr., Charles E. May | 2001-07-31 |
| 6268637 | Method of making air gap isolation by making a lateral EPI bridge for low K isolation advanced CMOS fabrication | Frederick N. Hause, Charles E. May | 2001-07-31 |
| 6265749 | Metal silicide transistor gate spaced from a semiconductor substrate by a ceramic gate dielectric having a high dielectric constant | Mark C. Gilmer | 2001-07-24 |
| 6261908 | Buried local interconnect | Frederick N. Hause, Charles E. May | 2001-07-17 |
| 6261909 | Semiconductor device having ultra shallow junctions and a reduced channel length and method for making same | H. Jim Fulford, Charles E. May | 2001-07-17 |
| 6258730 | Ultra-thin gate oxide formation using an N2O plasma | Sey-Ping Sun, Shengnian Song | 2001-07-10 |
| 6259142 | Multiple split gate semiconductor device and fabrication method | Robert Dawson, Frederick N. Hause, H. Jim Fulford, Mark W. Michael, Bradley T. Moore +1 more | 2001-07-10 |
| 6258675 | High K gate electrode | H. James Fulford | 2001-07-10 |
| 6258680 | Integrated circuit gate conductor which uses layered spacers to produce a graded junction | H. Jim Fulford, Derick J. Wristers | 2001-07-10 |