Issued Patents All Time
Showing 76–100 of 608 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11342339 | Method of making six transistor SRAM cell using connections between 3D transistor stacks | H. Jim Fulford | 2022-05-24 |
| 11302587 | Method for fabricating a 3D semiconductor apparatus having two vertically disposed seminconductor devices | H. Jim Fulford | 2022-04-12 |
| 11282828 | High density architecture design for 3D logic and 3D memory circuits | H. Jim Fulford | 2022-03-22 |
| 11276704 | Device and method of forming with three-dimensional memory and three-dimensional logic | H. Jim Fulford | 2022-03-15 |
| 11264289 | Method for threshold voltage tuning through selective deposition of high-K metal gate (HKMG) film stacks | Jeffrey Smith, Kandabara Tapily, Lars Liebmann, Daniel Chanemougame, H. Jim Fulford +1 more | 2022-03-01 |
| 11264285 | Method for forming film stacks with multiple planes of transistors having different transistor architectures | Jim Fulford | 2022-03-01 |
| 11251159 | High performance CMOS using 3D device layout | H. Jim Fulford | 2022-02-15 |
| 11251080 | Method of making 3D circuits with integrated stacked 3D metal lines for high density circuits | H. Jim Fulford, Anton J. deVilliers | 2022-02-15 |
| 11222964 | Multiple planes of transistors with different transistor architectures to enhance 3D logic and memory circuits | H. Jim Fulford | 2022-01-11 |
| 11195832 | High performance nanosheet fabrication method with enhanced high mobility channel elements | H. Jim Fulford | 2021-12-07 |
| 11177250 | Method for fabrication of high density logic and memory for advanced circuit architecture | H. Jim Fulford, Jeffrey Smith, Lars Liebmann, Daniel Chanemougame | 2021-11-16 |
| 11171208 | High performance circuit applications using stacked 3D metal lines | H. Jim Fulford, Anton J. deVilliers | 2021-11-09 |
| 11139213 | Method of making 3D source drains with hybrid stacking for optimum 3D logic layout | H. Jim Fulford | 2021-10-05 |
| 11133310 | Method of making multiple nano layer transistors to enhance a multiple stack CFET performance | H. Jim Fulford | 2021-09-28 |
| 11114346 | High density logic formation using multi-dimensional laser annealing | H. Jim Fulford, Jeffrey Smith, Lars Liebmann, Daniel Chanemougame | 2021-09-07 |
| 11107733 | Multi-dimensional planes of logic and memory formation using single crystal silicon orientations | H. Jim Fulford, Jeffrey Smith, Lars Liebmann, Daniel Chanemougame | 2021-08-31 |
| 11069616 | Horizontal programmable conducting bridges between conductive lines | H. Jim Fulford, Anton J. deVilliers | 2021-07-20 |
| 7832649 | Method of making a plurality of protected devices in communication with a background device | Dayton S. Whites, Dayton E. Whites, James E. Walters | 2010-11-16 |
| 7282773 | Semiconductor device with high-k dielectric layer | Hong Li | 2007-10-16 |
| 7138680 | Memory device with floating gate stack | Hong Li | 2006-11-21 |
| 6979878 | Isolation structure having implanted silicon atoms at the top corner of the isolation trench filling vacancies and interstitial sites | H. Jim Fulford, Derick J. Wristers | 2005-12-27 |
| 6911707 | Ultrathin high-K gate dielectric with favorable interface properties for improved semiconductor device performance | Dim-Lee Kwong, H. Jim Fulford | 2005-06-28 |
| 6767794 | Method of making ultra thin oxide formation using selective etchback technique integrated with thin nitride layer for high performance MOSFET | Michael Allen, H. James Fulford | 2004-07-27 |
| 6743688 | High performance MOSFET with modulated channel gate thickness | H. James Fulford, Charles E. May | 2004-06-01 |
| 6727569 | Method of making enhanced trench oxide with low temperature nitrogen integration | Mark C. Gilmer, Robert Paiz | 2004-04-27 |