Issued Patents All Time
Showing 101–125 of 608 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6674135 | Semiconductor structure having elevated salicided source/drain regions and metal gate electrode on nitride/oxide dielectric | Jon D. Cheek, Derick J. Wristers | 2004-01-06 |
| 6661057 | Tri-level segmented control transistor and fabrication method | Robert Dawson, Frederick N. Hause, H. Jim Fulford, Mark W. Michael, Bradley T. Moore +1 more | 2003-12-09 |
| 6661061 | Integrated circuit with differing gate oxide thickness | Fred N. Hause | 2003-12-09 |
| 6638829 | Semiconductor structure having a metal gate electrode and elevated salicided source/drain regions and a method for manufacture | Jon D. Cheek, Derick J. Wristers | 2003-10-28 |
| 6603180 | Semiconductor device having large-area silicide layer and process of fabrication thereof | H. Jim Fulford | 2003-08-05 |
| 6552776 | Photolithographic system including light filter that compensates for lens error | Derick J. Wristers, Robert Dawson, H. Jim Fulford, Frederick N. Hause, Bradley T. Moore +1 more | 2003-04-22 |
| 6531364 | Advanced fabrication technique to form ultra thin gate dielectric using a sacrificial polysilicon seed layer | H. Jim Fulford, Charles E. May | 2003-03-11 |
| 6504218 | Asymmetrical N-channel and P-channel devices | Daniel Kadosh | 2003-01-07 |
| 6483157 | Asymmetrical transistor having a barrier-incorporated gate oxide and a graded implant only in the drain-side junction area | H. Jim Fulford | 2002-11-19 |
| 6469316 | Test structure to monitor the effects of polysilicon pre-doping | John J. Bush, David E. Brown | 2002-10-22 |
| 6451657 | Transistor with an ultra short channel length defined by a laterally diffused nitrogen implant | H. Jim Fulford, Charles E. May | 2002-09-17 |
| 6433400 | Semiconductor fabrication employing barrier atoms incorporated at the edges of a trench isolation structure | H. Jim Fulford, Derick J. Wristers | 2002-08-13 |
| 6429052 | Method of making high performance transistor with a reduced width gate electrode and device comprising same | John J. Bush, Frederick N. Hause | 2002-08-06 |
| 6420220 | Method of forming electrode for high performance semiconductor devices | H. Jim Fulford, Charles E. May | 2002-07-16 |
| 6420730 | Elevated transistor fabrication technique | Daniel Kadosh, Michael Duane | 2002-07-16 |
| 6417539 | High density memory cell assembly and methods | Derick J. Wristers, Jon D. Cheek | 2002-07-09 |
| 6410967 | Transistor having enhanced metal silicide and a self-aligned gate electrode | Frederick N. Hause, Charles E. May | 2002-06-25 |
| 6410409 | Implanted barrier layer for retarding upward diffusion of substrate dopant | Robert Dawson, H. Jim Fulford, Frederick N. Hause, Mark W. Michael, Bradley T. Moore +1 more | 2002-06-25 |
| 6403445 | Enhanced trench isolation structure | Frederick N. Hause, Charles E. May | 2002-06-11 |
| 6388298 | Detached drain MOSFET | H. Jim Fulford | 2002-05-14 |
| 6383874 | In-situ stack for high volume production of isolation regions | Sey-Ping Sun, Robert Anderson | 2002-05-07 |
| 6383872 | Parallel and series-coupled transistors having gate conductors formed on sidewall surfaces of a sacrificial structure | Daniel Kadosh, Jon D. Cheek | 2002-05-07 |
| 6380554 | Test structure for electrically measuring the degree of misalignment between successive layers of conductors | John J. Bush, H. Jim Fulford | 2002-04-30 |
| 6380055 | Dopant diffusion-retarding barrier region formed within polysilicon gate layer | Robert Dawson, H. Jim Fulford, Frederick N. Hause, Mark W. Michael, Bradley T. Moore +1 more | 2002-04-30 |
| 6373113 | Nitrogenated gate structure for improved transistor performance and method for making same | Mark C. Gilmer | 2002-04-16 |