Issued Patents All Time
Showing 151–175 of 608 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6258675 | High K gate electrode | H. James Fulford | 2001-07-10 |
| 6258646 | CMOS integrated circuit and method for implanting NMOS transistor areas prior to implanting PMOS transistor areas to optimize the thermal diffusivity thereof | H. Jim Fulford, Derick J. Wristers | 2001-07-10 |
| 6259118 | Ultra high density NOR gate using a stacked transistor arrangement | Daniel Kadosh | 2001-07-10 |
| 6255698 | Separately optimized gate structures for n-channel and p-channel transistors in an integrated circuit | H. Jim Fulford | 2001-07-03 |
| 6252283 | CMOS transistor design for shared N+/P+ electrode with enhanced device performance | Dim-Lee Kwong, Frederick N. Hause | 2001-06-26 |
| 6251800 | Ultrathin deposited gate dielectric formation using low-power, low-pressure PECVD for improved semiconductor device performance | Sey-Ping Sun, Charles E. May | 2001-06-26 |
| 6248252 | Method of fabricating sub-micron metal lines | Thien T. Nguyen | 2001-06-19 |
| 6245652 | Method of forming ultra thin gate dielectric for high performance semiconductor devices | Dim-Lee Kwong, H. Jim Fulford | 2001-06-12 |
| 6245638 | Trench and gate dielectric formation for semiconductor devices | H. Jim Fulford, Charles E. May | 2001-06-12 |
| 6242317 | High quality isolation structure formation | Thien T. Nguyen, Charles E. May | 2001-06-05 |
| 6239476 | Integrated circuit isolation structure employing a protective layer and method for making same | Thomas E. Spikes, Jr., H. Jim Fulford | 2001-05-29 |
| 6239467 | Method of forming semiconductor devices using gate electrode length and spacer width for controlling drive current strength | H. Jim Fulford, Anthony J. Toprac | 2001-05-29 |
| 6232637 | Semiconductor fabrication having multi-level transistors and high density interconnect therebetween | Daniel Kadosh | 2001-05-15 |
| 6228724 | Method of making high performance MOSFET with enhanced gate oxide integration and device formed thereby | Thomas E. Spikes, Jr., H. Jim Fulford | 2001-05-08 |
| 6228663 | Method of forming semiconductor devices using gate insulator thickness and channel length for controlling drive current strength | H. Jim Fulford, Anthony J. Toprac | 2001-05-08 |
| 6225646 | Integrated circuit incorporating a memory cell and a transistor elevated above an insulating base | H. Jim Fulford | 2001-05-01 |
| 6225201 | Ultra short transistor channel length dictated by the width of a sidewall spacer | Derrick J. Wristers, Jon D. Cheek, Thomas E. Spikes, Jr. | 2001-05-01 |
| 6225188 | Self aligned method for differential oxidation rate at shallow trench isolation edge | Derick J. Wristers, H. Jim Fulford | 2001-05-01 |
| 6225168 | Semiconductor device having metal gate electrode and titanium or tantalum nitride gate dielectric barrier layer and process of fabrication thereof | H. Jim Fulford, Charles E. May, Fred N. Hause, Dim-Lee Kwong | 2001-05-01 |
| 6225151 | Nitrogen liner beneath transistor source/drain regions to retard dopant diffusion | Robert Dawson, H. Jim Fulford, Frederick N. Hause, Daniel Kadosh, Mark W. Michael +2 more | 2001-05-01 |
| 6222240 | Salicide and gate dielectric formed from a single layer of refractory metal | H. Jim Fulford | 2001-04-24 |
| 6222230 | Method of making an elevated source/drain with enhanced graded sidewalls for transistor scaling integrated with spacer formation | H. Jim Fulford, Charles E. May | 2001-04-24 |
| 6218720 | Semiconductor topography employing a nitrogenated shallow trench isolation structure | Dim-Lee Kwong, H. Jim Fulford | 2001-04-17 |
| 6218251 | Asymmetrical IGFET devices with spacers formed by HDP techniques | Daniel Kadosh | 2001-04-17 |
| 6214690 | Method of forming a semiconductor device having integrated electrode and isolation region formation | Mark C. Gilmer | 2001-04-10 |