Issued Patents All Time
Showing 201–225 of 608 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6187620 | Integrated circuit having sacrificial spacers for producing graded NMOS source/drain junctions possibly dissimilar from PMOS source/drain junctions | H. Jim Fulford, Derick J. Wristers | 2001-02-13 |
| 6184566 | Method and structure for isolating semiconductor devices after transistor formation | Fred N. Hause, H. Jim Fulford | 2001-02-06 |
| 6180987 | Integrated circuit transistor with low-resistivity source/drain structures at least partially recessed within a dielectric base layer | H. Jim Fulford | 2001-01-30 |
| 6180465 | Method of making high performance MOSFET with channel scaling mask feature | Thien T. Nguyen | 2001-01-30 |
| 6177687 | Semiconductor device having gate electrode shared between two sets of active regions and fabrication thereof | H. Jim Fulford | 2001-01-23 |
| 6175144 | Advanced isolation structure for high density semiconductor devices | Mark C. Gilmer | 2001-01-16 |
| 6174794 | Method of making high performance MOSFET with polished gate and source/drain feature | Mark C. Gilmer | 2001-01-16 |
| 6172407 | Source/drain and lightly doped drain formation at post interlevel dielectric isolation with high-K gate electrode design | Mark C. Gilmer | 2001-01-09 |
| 6172402 | Integrated circuit having transistors that include insulative punchthrough regions and method of formation | Mark C. Gilmer, Daniel Kadosh | 2001-01-09 |
| 6172381 | Source/drain junction areas self aligned between a sidewall spacer and an etched lateral sidewall | Daniel Kadosh | 2001-01-09 |
| 6168958 | Semiconductor structure having multiple thicknesses of high-K gate dielectrics and process of manufacture therefor | H. Jim Fulford, Charles E. May | 2001-01-02 |
| 6169306 | Semiconductor devices comprised of one or more epitaxial layers | Mark C. Gilmer | 2001-01-02 |
| 6169006 | Semiconductor device having grown oxide spacers and method of manufacture thereof | H. Jim Fulford, Charles E. May | 2001-01-02 |
| 6165314 | Apparatus for performing jet vapor reduction of the thickness of process layers | Mark C. Gilmer | 2000-12-26 |
| 6166354 | System and apparatus for in situ monitoring and control of annealing in semiconductor fabrication | Frederick N. Hause, Robert Dawson, H. Jim Fulford, Mark W. Michael, Bradley T. Moore +1 more | 2000-12-26 |
| 6165858 | Enhanced silicidation formation for high speed MOS device by junction grading with dual implant dopant species | Fred N. Hause, Jon Cheek | 2000-12-26 |
| 6162687 | Method of manufacturing semiconductor device having oxide-nitride gate insulating layer | H. Jim Fulford, Charles E. May | 2000-12-19 |
| 6162688 | Method of fabricating a transistor with a dielectric underlayer and device incorporating same | H. Jim Fulford, Derick J. Wristers | 2000-12-19 |
| 6163060 | Semiconductor device with a composite gate dielectric layer and gate barrier layer and method of making same | Mark C. Gilmer | 2000-12-19 |
| 6162692 | Integration of a diffusion barrier layer and a counter dopant region to maintain the dopant level within the junctions of a transistor | Derrick J. Wristers, Thien T. Nguyen | 2000-12-19 |
| 6162694 | Method of forming a metal gate electrode using replaced polysilicon structure | Jon D. Cheek, Derick J. Wristers | 2000-12-19 |
| 6163059 | Integrated circuit including source implant self-aligned to contact via | Frederick N. Hause | 2000-12-19 |
| 6160300 | Multi-layer gate conductor having a diffusion barrier in the bottom layer | Derick J. Wristers, Charles E. May | 2000-12-12 |
| 6160316 | Integrated circuit utilizing an air gap to reduce capacitance between adjacent metal linewidths | Thomas E. Spikes, Jr., Robert Paiz | 2000-12-12 |
| 6159814 | Spacer formation by poly stack dopant profile design | Fred N. Hause, Charles E. May | 2000-12-12 |