Issued Patents All Time
Showing 251–275 of 608 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6127235 | Method for making asymmetrical gate oxide thickness in channel MOSFET region | H. James Fulford, Charles E. May | 2000-10-03 |
| 6127234 | Ultra shallow extension formation using disposable spacers | Frederick N. Hause, Charles E. May | 2000-10-03 |
| 6124217 | In-situ SiON deposition/bake/TEOS deposition process for reduction of defects in interlevel dielectric for integrated circuit interconnects | Sey-Ping Sun, Minh Van Ngo | 2000-09-26 |
| 6124620 | Incorporating barrier atoms into a gate dielectric using gas cluster ion beam implantation | Mark C. Gilmer | 2000-09-26 |
| 6124172 | Method of making a semiconductor device having source/drain structures with self-aligned heavily-doped and lightly-doped regions | Mark C. Gilmer | 2000-09-26 |
| 6124174 | Spacer structure as transistor gate | Thomas E. Spikes, Jr. | 2000-09-26 |
| 6124175 | Rapid thermal anneal with a gaseous dopant species | H. James Fulford | 2000-09-26 |
| 6124188 | Semiconductor device and fabrication method using a germanium sacrificial gate electrode plug | H. Jim Fulford | 2000-09-26 |
| 6121094 | Method of making a semiconductor device with a multi-level gate structure | Mark C. Gilmer | 2000-09-19 |
| 6121099 | Selective spacer formation for optimized silicon area reduction | H. Jim Fulford | 2000-09-19 |
| 6121631 | Test structure to determine the effect of LDD length upon transistor performance | Fred N. Hause, H. Jim Fulford | 2000-09-19 |
| 6121643 | Semiconductor device having a group of high performance transistors and method of manufacture thereof | Daniel Kadosh | 2000-09-19 |
| 6117760 | Method of making a high density interconnect formation | H. Jim Fulford, Fred N. Hause | 2000-09-12 |
| 6118137 | Test structure responsive to electrical signals for determining lithographic misalignment of conductors relative to vias | H. Jim Fulford, Fred N. Hause | 2000-09-12 |
| 6117742 | Method for making a high performance transistor | Fred N. Hause | 2000-09-12 |
| 6118163 | Transistor with integrated poly/metal gate electrode | Derick J. Wristers, Jon D. Cheek | 2000-09-12 |
| 6117739 | Semiconductor device with layered doped regions and methods of manufacture | Fred N. Hause, Charles E. May | 2000-09-12 |
| 6114229 | Polysilicon gate electrode critical dimension and drive current control in MOS transistor fabrication | Frederick N. Hause, Charles E. May | 2000-09-05 |
| 6114251 | Method of fabrication for ultra thin nitride liner in silicon trench isolation | Thien T. Nguyen, Frederick N. Hause | 2000-09-05 |
| 6114228 | Method of making a semiconductor device with a composite gate dielectric layer and gate barrier layer | Mark C. Gilmer | 2000-09-05 |
| 6111260 | Method and apparatus for in situ anneal during ion implant | Robert Dawson, H. Jim Fulford, Frederick N. Hause, Mark W. Michael, Bradley T. Moore +1 more | 2000-08-29 |
| 6111292 | Semiconductor fabrication employing self-aligned sidewall spacers laterally adjacent to a transistor gate | Mark C. Gilmer | 2000-08-29 |
| 6110786 | Semiconductor device having elevated gate electrode and elevated active regions and method of manufacture thereof | Jon D. Cheek, John J. Bush | 2000-08-29 |
| 6111298 | Etch stop layer formed within a multi-layered gate conductor to provide for reduction of channel length | Daniel Kadosh, Michael Duane | 2000-08-29 |
| 6110784 | Method of integration of nitrogen bearing high K film | Mark C. Gilmer | 2000-08-29 |