Issued Patents All Time
Showing 276–300 of 608 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6110786 | Semiconductor device having elevated gate electrode and elevated active regions and method of manufacture thereof | Jon D. Cheek, John J. Bush | 2000-08-29 |
| 6107129 | Integrated circuit having multiple LDD and/or source/drain implant steps to enhance circuit performance | Fred N. Hause, H. Jim Fulford | 2000-08-22 |
| 6107130 | CMOS integrated circuit having a sacrificial metal spacer for producing graded NMOS source/drain junctions dissimilar from PMOS source/drain junctions | H. Jim Fulford, Derick J. Wristers | 2000-08-22 |
| 6106618 | Photoresist application for a circlet wafer | Mark C. Gilmer | 2000-08-22 |
| 6107146 | Method of replacing epitaxial wafers in CMOS process | Mark C. Gilmer | 2000-08-22 |
| 6107150 | Method of making high performance transistors using channel modulated implant for ultra thin oxide formation | H. Jim Fulford | 2000-08-22 |
| 6104069 | Semiconductor device having an elevated active region formed in an oxide trench | Michael Duane, Daniel Kadosh | 2000-08-15 |
| 6104077 | Semiconductor device having gate electrode with a sidewall air gap | Derick J. Wristers, Jon D. Cheek | 2000-08-15 |
| 6104064 | Asymmetrical transistor structure | Daniel Kadosh, Michael Duane, Jon D. Cheek, Fred N. Hause, Robert Dawson +1 more | 2000-08-15 |
| 6104063 | Multiple spacer formation/removal technique for forming a graded junction | H. Jim Fulford, Derick J. Wristers | 2000-08-15 |
| 6103559 | Method of making disposable channel masking for both source/drain and LDD implant and subsequent gate fabrication | H. Jim Fulford, Derick J. Wristers | 2000-08-15 |
| 6100204 | Method of making ultra thin gate oxide using aluminum oxide | Mark C. Gilmer, Thomas E. Spikes, Jr. | 2000-08-08 |
| 6100173 | Forming a self-aligned silicide gate conductor to a greater thickness than junction silicide structures using a dual-salicidation process | H. Jim Fulford, Charles E. May | 2000-08-08 |
| 6100148 | Semiconductor device having a liner defining the depth of an active region, and fabrication thereof | Derick J. Wristers, Jim Fulford | 2000-08-08 |
| 6100147 | Method for manufacturing a high performance transistor with self-aligned dopant profile | Mark C. Gilmer | 2000-08-08 |
| 6100146 | Method of forming trench transistor with insulative spacers | Robert Dawson, H. Jim Fulford, Frederick N. Hause, Mark W. Michael, Bradley T. Moore +1 more | 2000-08-08 |
| 6099387 | CMP of a circlet wafer using disc-like brake polish pads | Mark C. Gilmer | 2000-08-08 |
| 6097096 | Metal attachment method and structure for attaching substrates at low temperatures | Fred N. Hause, Daniel Kadosh | 2000-08-01 |
| 6097062 | Optimized trench edge formation integrated with high quality gate formation | H. Jim Fulford, Derick J. Wristers | 2000-08-01 |
| 6096659 | Manufacturing process for reducing feature dimensions in a semiconductor | Mark C. Gilmer | 2000-08-01 |
| 6096658 | Semiconductor device having in-doped indium oxide etch stop | Mark C. Gilmer | 2000-08-01 |
| 6096639 | Method of forming a local interconnect by conductive layer patterning | Robert Dawson, Frederick N. Hause, H. Jim Fulford, Mark W. Michael, Bradley T. Moore +1 more | 2000-08-01 |
| 6096615 | Method of forming a semiconductor device having narrow gate electrode | Derick J. Wristers | 2000-08-01 |
| 6096591 | Method of making an IGFET and a protected resistor with reduced processing steps | Daniel Kadosh, Derick J. Wristers | 2000-08-01 |
| 6093611 | Oxide liner for high reliability with reduced encroachment of the source/drain region | Derick J. Wristers, H. Jim Fulford | 2000-07-25 |