Issued Patents All Time
Showing 226–250 of 608 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6159814 | Spacer formation by poly stack dopant profile design | Fred N. Hause, Charles E. May | 2000-12-12 |
| 6153477 | Ultra short transistor channel length formed using a gate dielectric having a relatively high dielectric constant | Mark C. Gilmer | 2000-11-28 |
| 6152075 | Method and system for heating semiconductor wafers | Mark C. Gilmer | 2000-11-28 |
| 6150708 | Advanced CMOS circuitry that utilizes both sides of a wafer surface for increased circuit density | H. Jim Fulford, Charles E. May | 2000-11-21 |
| 6148832 | Method and apparatus for in-situ cleaning of polysilicon-coated quartz furnaces | Mark C. Gilmer, Robert Paiz | 2000-11-21 |
| 6150286 | Method of making an ultra thin silicon nitride film | Sey-Ping Sun, Shengnian Song | 2000-11-21 |
| 6150695 | Multilevel transistor formation employing a local substrate formed within a shallow trench | Daniel Kadosh, Derick J. Wristers | 2000-11-21 |
| 6150222 | Method of making a high performance transistor with elevated spacer formation and self-aligned channel regions | Thien T. Nguyen, Charles E. May | 2000-11-21 |
| 6146934 | Semiconductor device with asymmetric PMOS source/drain implant and method of manufacture thereof | H. Jim Fulford, Jack Lee | 2000-11-14 |
| 6146978 | Integrated circuit having an interlevel interconnect coupled to a source/drain region(s) with source/drain region(s) boundary overlap and reduced parasitic capacitance | Mark W. Michael, Robert Dawson, H. Jim Fulford, Frederick N. Hause, Bradley T. Moore +1 more | 2000-11-14 |
| 6146983 | Method of making semiconductor device having sacrificial salicidation layer | Frederick N. Hause, Charles E. May | 2000-11-14 |
| 6147004 | Jet vapor reduction of the thickness of process layers | Mark C. Gilmer | 2000-11-14 |
| 6144071 | Ultrathin silicon nitride containing sidewall spacers for improved transistor performance | H. Jim Fulford, Charles E. May | 2000-11-07 |
| 6140190 | Method and structure for elevated source/drain with polished gate electrode insulated gate field effect transistors | Thomas E. Spikes, Jr., Michael Duane | 2000-10-31 |
| 6140191 | Method of making high performance MOSFET with integrated simultaneous formation of source/drain and gate regions | Mark C. Gilmer, Robert Paiz | 2000-10-31 |
| 6140674 | Buried trench capacitor | Frederick N. Hause, Charles E. May | 2000-10-31 |
| 6140688 | Semiconductor device with self-aligned metal-containing gate | Sey-Ping Sun | 2000-10-31 |
| 6140691 | Trench isolation structure having a low K dielectric material isolated from a silicon-based substrate | H. Jim Fulford, Charles E. May | 2000-10-31 |
| 6140163 | Method and apparatus for upper level substrate isolation integrated with bulk silicon | Daniel Kadosh, Thomas E. Spikes, Jr. | 2000-10-31 |
| 6140167 | High performance MOSFET and method of forming the same using silicidation and junction implantation prior to gate formation | Mark C. Gilmer, Frederick N. Hause | 2000-10-31 |
| 6140677 | Semiconductor topography for a high speed MOSFET having an ultra narrow gate | Frederick N. Hause | 2000-10-31 |
| 6137182 | Method of reducing via and contact dimensions beyond photolithography equipment limits | Fred N. Hause, Robert Dawson | 2000-10-24 |
| 6130164 | Semiconductor device having gate oxide formed by selective oxide removal and method of manufacture thereof | Mark C. Gilmer | 2000-10-10 |
| 6130454 | Gate conductor formed within a trench bounded by slanted sidewalls | John J. Bush, Jon D. Cheek | 2000-10-10 |
| 6127235 | Method for making asymmetrical gate oxide thickness in channel MOSFET region | H. James Fulford, Charles E. May | 2000-10-03 |