Issued Patents All Time
Showing 326–350 of 608 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6069387 | Lightly doped drain formation integrated with source/drain formation for high-performance transistor formation | — | 2000-05-30 |
| 6069398 | Thin film resistor and fabrication method thereof | Daniel Kadosh, Frederick N. Hause | 2000-05-30 |
| 6069384 | Integrated circuit including vertical transistors with spacer gates having selected gate widths | Frederick N. Hause | 2000-05-30 |
| 6069046 | Transistor fabrication employing implantation of dopant into junctions without subjecting sidewall surfaces of a gate conductor to ion bombardment | Daniel Kadosh, Michael Duane | 2000-05-30 |
| 6066519 | Semiconductor device having an outgassed oxide layer and fabrication thereof | Mark C. Gilmer | 2000-05-23 |
| 6064102 | Semiconductor device having gate electrodes with different gate insulators and fabrication thereof | H. Jim Fulford, Thomas E. Spikes, Jr. | 2000-05-16 |
| 6063679 | Spacer formation for graded dopant profile having a triangular geometry | Fred N. Hause, Charles E. May | 2000-05-16 |
| 6060767 | Semiconductor device having fluorine bearing sidewall spacers and method of manufacture thereof | Mark C. Gilmer | 2000-05-09 |
| 6060369 | Nitrogen bearing sacrificial oxide with subsequent high nitrogen dopant profile for high performance MOSFET | Derick J. Wristers, H. Jim Fulford | 2000-05-09 |
| 6060345 | Method of making NMOS and PMOS devices with reduced masking steps | Frederick N. Hause, Robert Dawson, H. Jim Fulford, Mark W. Michael, Bradley T. Moore +1 more | 2000-05-09 |
| 6060733 | Formation of lightly doped regions under a gate having a reduced gate oxide | H. James Fulford | 2000-05-09 |
| 6057584 | Semiconductor device having a tri-layer gate insulating dielectric | Mark C. Gilmer, H. Jim Fulford, Jack Lee | 2000-05-02 |
| 6057583 | Transistor with low resistance metal source and drain vertically displaced from the channel | H. Jim Fulford | 2000-05-02 |
| 6057209 | Semiconductor device having a nitrogen bearing isolation region | Mark C. Gilmer | 2000-05-02 |
| 6057194 | Method of forming trench transistor in combination with trench array | H. Jim Fulford, Derick J. Wristers | 2000-05-02 |
| 6054385 | Elevated local interconnect and contact structure | Fred N. Hause | 2000-04-25 |
| 6054374 | Method of scaling dielectric thickness in a semiconductor process with ion implantation | H. James Fulford | 2000-04-25 |
| 6054364 | Chemical mechanical polishing etch stop for trench isolation | Mark C. Gilmer | 2000-04-25 |
| 6051876 | Semiconductor device with a graded passivation layer | Sey-Ping Sun, Daniel Kadosh | 2000-04-18 |
| 6051865 | Transistor having a barrier layer below a high permittivity gate dielectric | Mark C. Gilmer, Derick J. Wristers | 2000-04-18 |
| 6051863 | Transistor gate conductor having sidewall surfaces upon which a spacer having a profile that substantially prevents silicide bridging is formed | Fred N. Hause, Charles E. May | 2000-04-18 |
| 6051487 | Semiconductor device fabrication using a sacrificial plug for defining a region for a gate electrode | H. Jim Fulford, Mark C. Gilmer, Robert Paiz | 2000-04-18 |
| 6051486 | Method and structure for replaceable gate electrode in insulated gate field effect transistors | — | 2000-04-18 |
| 6051471 | Method for making asymmetrical N-channel and symmetrical P-channel devices | Derick J. Wristers, H. Jim Fulford | 2000-04-18 |
| 6051459 | Method of making N-channel and P-channel IGFETs using selective doping and activation for the N-channel gate | Daniel Kadosh, Frederick N. Hause, Derick J. Wristers | 2000-04-18 |