Issued Patents All Time
Showing 351–375 of 608 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6049133 | Semiconductor fabrication employing concurrent diffusion barrier and salicide formation | Fred N. Hause | 2000-04-11 |
| 6048803 | Method of fabricating a semiconductor device having fluorine bearing oxide between conductive lines | Daniel Kadosh | 2000-04-11 |
| 6048766 | Flash memory device having high permittivity stacked dielectric and fabrication thereof | Mark C. Gilmer, Thomas E. Spikes, Jr. | 2000-04-11 |
| 6048785 | Semiconductor fabrication method of combining a plurality of fields defined by a reticle image using segment stitching | H. Jim Fulford, Robert Dawson, Frederick N. Hause, Mark W. Michael, Bradley T. Moore +1 more | 2000-04-11 |
| 6046089 | Selectively sized spacers | Fred N. Hause, Charles E. May | 2000-04-04 |
| 6046471 | Ultra shallow junction depth transistors | Fred N. Hause, Daniel Kadosh | 2000-04-04 |
| 6043533 | Method of integrating Ldd implantation for CMOS device fabrication | Fred N. Hause, Robert Paiz | 2000-03-28 |
| 6043157 | Semiconductor device having dual gate electrode material and process of fabrication thereof | Mark C. Gilmer | 2000-03-28 |
| 6040602 | Formation of lightly doped regions under a gate | H. James Fulford | 2000-03-21 |
| 6040207 | Oxide formation technique using thin film silicon deposition | Mark C. Gilmer | 2000-03-21 |
| 6040607 | Self aligned method for differential oxidation rate at shallow trench isolation edge | Derick J. Wristers, H. Jim Fulford | 2000-03-21 |
| 6040220 | Asymmetrical transistor formed from a gate conductor of unequal thickness | Daniel Kadosh, Michael Duane | 2000-03-21 |
| 6037629 | Trench transistor and isolation trench | Daniel Kadosh, Jon D. Cheek | 2000-03-14 |
| 6037244 | Method of manufacturing a semiconductor device using advanced contact formation | Thomas E. Spikes, Jr., Robert Paiz, Frederick N. Hause, Sey-Ping Sun | 2000-03-14 |
| 6033943 | Dual gate oxide thickness integrated circuit and process for making same | — | 2000-03-07 |
| 6030860 | Elevated substrate formation and local interconnect integrated fabrication | Daniel Kadosh, Michael Duane | 2000-02-29 |
| 6030752 | Method of stitching segments defined by adjacent image patterns during the manufacture of a semiconductor device | H. Jim Fulford, Robert Dawson, Frederick N. Hause, Mark W. Michael, Bradley T. Moore +1 more | 2000-02-29 |
| 6027992 | Semiconductor device having a gallium and nitrogen containing barrier layer and method of manufacturing thereof | Mark C. Gilmer | 2000-02-22 |
| 6027978 | Method of making an IGFET with a non-uniform lateral doping profile in the channel region | Michael Duane, Daniel Kadosh | 2000-02-22 |
| 6027976 | Process for making semiconductor device having nitride at silicon and polysilicon interfaces | Mark C. Gilmer | 2000-02-22 |
| 6027964 | Method of making an IGFET with a selectively doped gate in combination with a protected resistor | Daniel Kadosh, Michael Duane | 2000-02-22 |
| 6025633 | Multi-level transistor fabrication method having an inverted, upper level transistor which shares a gate conductor with a non-inverted, lower level transistor | Daniel Kadosh | 2000-02-15 |
| 6025238 | Semiconductor device having an nitrogen-rich punchthrough region and fabrication thereof | — | 2000-02-15 |
| 6020232 | Process of fabricating transistors having source and drain regions laterally displaced from the transistors gate | H. Jim Fulford | 2000-02-01 |
| 6020260 | Method of fabricating a semiconductor device having nitrogen-bearing gate electrode | — | 2000-02-01 |