Issued Patents All Time
Showing 401–425 of 608 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5985706 | Polishing method for thin gates dielectric in semiconductor process | Mark C. Gilmer | 1999-11-16 |
| 5986283 | Test structure for determining how lithographic patterning of a gate conductor affects transistor properties | John J. Bush, Jon D. Cheek | 1999-11-16 |
| 5985743 | Single mask substrate doping process for CMOS integrated circuits | — | 1999-11-16 |
| 5985724 | Method for forming asymmetrical p-channel transistor having nitrided oxide patterned to selectively form a sidewall spacer | Daniel Kadosh | 1999-11-16 |
| 5981368 | Enhanced shallow junction design by polysilicon line width reduction using oxidation with integrated spacer formation | H. Jim Fulford, Charles E. May | 1999-11-09 |
| 5981365 | Stacked poly-oxide-poly gate for improved silicide formation | Jon D. Cheek, Derick J. Wristers | 1999-11-09 |
| 5981363 | Method and apparatus for high performance transistor devices | H. Jim Fulford, Charles E. May | 1999-11-09 |
| 5981357 | Semiconductor trench isolation with improved planarization methodology | Fred N. Hause, Robert Dawson, Charles E. May, Kuang-Yeh Chang | 1999-11-09 |
| 5977602 | Semiconductor device having an oxygen-rich punchthrough region extending through the length of the active region | H. Jim Fulford | 1999-11-02 |
| 5976956 | Method of controlling dopant concentrations using transient-enhanced diffusion prior to gate formation in a device | Derick J. Wristers, Robert Dawson, H. Jim Fulford, Frederick N. Hause, Mark W. Michael +1 more | 1999-11-02 |
| 5976952 | Implanted isolation structure formation for high density CMOS integrated circuits | Mark C. Gilmer | 1999-11-02 |
| 5976938 | Method of making enhancement-mode and depletion-mode IGFETs with different gate thicknesses | Frederick N. Hause | 1999-11-02 |
| 5976924 | Method of making a self-aligned disposable gate electrode for advanced CMOS design | Derick J. Wristers, H. Jim Fulford | 1999-11-02 |
| 5970375 | Semiconductor fabrication employing a local interconnect | Daniel Kadosh, Thomas E. Spikes, Jr. | 1999-10-19 |
| 5970331 | Method of making a plug transistor | Frederick N. Hause | 1999-10-19 |
| 5970354 | Poly recessed fabrication method for defining high performance MOSFETS | Fred N. Hause, H. Jim Fulford | 1999-10-19 |
| 5970350 | Semiconductor device having a thin gate oxide and method of manufacture thereof | Thomas, Jr. E. Spikes, Robert Paiz | 1999-10-19 |
| 5970349 | Semiconductor device having one or more asymmetric background dopant regions and method of manufacture thereof | Jon Cheek, Michael Duane | 1999-10-19 |
| 5970347 | High performance mosfet transistor fabrication technique | H. Jim Fulford | 1999-10-19 |
| 5969407 | MOSFET device with an amorphized source | H. Jim Fulford, Derick J. Wristers | 1999-10-19 |
| 5969394 | Method and structure for high aspect gate and short channel length insulated gate field effect transistors | Daniel Kadosh | 1999-10-19 |
| 5963810 | Semiconductor device having nitrogen enhanced high permittivity gate insulating layer and fabrication thereof | Mark C. Gilmer, Thomas E. Spikes, Jr. | 1999-10-05 |
| 5963809 | Asymmetrical MOSFET with gate pattern after source/drain formation | Michael Duane | 1999-10-05 |
| 5962914 | Reduced bird's beak field oxidation process using nitrogen implanted into active region | Fred N. Hause, Kuang-Yeh Chang | 1999-10-05 |
| 5962894 | Trench transistor with metal spacers | Robert Dawson, H. Jim Fulford, Frederick N. Hause, Mark W. Michael, Bradley T. Moore +1 more | 1999-10-05 |