Issued Patents All Time
Showing 451–475 of 608 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5933717 | Vertical transistor interconnect structure and fabrication method thereof | Frederick N. Hause | 1999-08-03 |
| 5933721 | Method for fabricating differential threshold voltage transistor pair | Frederick N. Hause, Daniel Kadosh | 1999-08-03 |
| 5933747 | Method and structure for an advanced isolation spacer shell | Thomas E. Spikes, Jr. | 1999-08-03 |
| 5929496 | Method and structure for channel length reduction in insulated gate field effect transistors | Thomas E. Spikes, Jr., Robert Paiz | 1999-07-27 |
| 5930632 | Process of fabricating a semiconductor device having cobalt niobate gate electrode structure | Mark C. Gilmer | 1999-07-27 |
| 5930634 | Method of making an IGFET with a multilevel gate | Frederick N. Hause, Robert Dawson, H. Jim Fulford, Mark W. Michael, Bradley T. Moore +1 more | 1999-07-27 |
| 5930642 | Transistor with buried insulative layer beneath the channel region | Bradley T. Moore, Robert Dawson, H. Jim Fulford, Frederick N. Hause, Mark W. Michael +1 more | 1999-07-27 |
| 5930620 | Resistance to gate dielectric breakdown at the edges of shallow trench isolation structures | Derrick J. Wristers, H. Jim Fulford | 1999-07-27 |
| 5926700 | Semiconductor fabrication having multi-level transistors and high density interconnect therebetween | Daniel Kadosh | 1999-07-20 |
| 5926693 | Two level transistor formation for optimum silicon utilization | Fred N. Hause, Jon D. Cheek | 1999-07-20 |
| 5926714 | Detached drain MOSFET | H. Jim Fulford | 1999-07-20 |
| 5923984 | Method of making enhancement-mode and depletion-mode IGFETS with different gate materials | Frederick N. Hause | 1999-07-13 |
| 5923949 | Semiconductor device having fluorine bearing sidewall spacers and method of manufacture thereof | Mark C. Gilmer | 1999-07-13 |
| 5923980 | Trench transistor with localized source/drain regions implanted through voids in trench | H. Jim Fulford, Frederick N. Hause | 1999-07-13 |
| 5923982 | Method of making asymmetrical transistor with lightly and heavily doped drain regions and ultra-heavily doped source region using two source/drain implant steps | Daniel Kadosh, Robert Dawson | 1999-07-13 |
| 5923983 | Integrated circuit gate conductor having a gate dielectric which is substantially resistant to hot carrier effects | H. Jim Fulford, Derick J. Wristers | 1999-07-13 |
| 5923992 | Integrated circuit formed with shallow isolation structures having nitride placed on the trench dielectric | Thomas E. Spikes, Jr., Fred N. Hause | 1999-07-13 |
| 5920103 | Asymmetrical transistor having a gate dielectric which is substantially resistant to hot carrier injection | H. Jim Fulford | 1999-07-06 |
| 5918133 | Semiconductor device having dual gate dielectric thickness along the channel and fabrication thereof | Robert Paiz | 1999-06-29 |
| 5918129 | Method of channel doping using diffusion from implanted polysilicon | H. Jim Fulford, Robert Dawson, Frederick N. Hause, Mark W. Michael, Bradley T. Moore +1 more | 1999-06-29 |
| 5918128 | Reduced channel length for a high performance CMOS transistor | John J. Bush | 1999-06-29 |
| 5918126 | Method of fabricating an integrated circuit having devices arranged with different device densities using a bias differential to form devices with a uniform size | H. Jim Fulford, Robert Dawson, Frederick N. Hause, Mark W. Michael, Bradley T. Moore +1 more | 1999-06-29 |
| 5916715 | Process of using electrical signals for determining lithographic misalignment of vias relative to electrically active elements | H. Jim Fulford, Fred N. Hause | 1999-06-29 |
| 5918130 | Transistor fabrication employing formation of silicide across source and drain regions prior to formation of the gate conductor | Fred N. Hause, H. Jim Fulford | 1999-06-29 |
| 5918134 | Method of reducing transistor channel length with oxidation inhibiting spacers | Fred N. Hause, H. Jim Fulford | 1999-06-29 |