Issued Patents All Time
Showing 476–500 of 608 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5913116 | Method of manufacturing an active region of a semiconductor by diffusing a dopant out of a sidewall spacer | Jon Cheek | 1999-06-15 |
| 5912493 | Enhanced oxidation for spacer formation integrated with LDD implantation | Fred N. Hause, Charles E. May | 1999-06-15 |
| 5912188 | Method of forming a contact hole in an interlevel dielectric layer using dual etch stops | Daniel Kadosh, Frederick N. Hause | 1999-06-15 |
| 5908315 | Method for forming a test structure to determine the effect of LDD length upon transistor performance | Fred N. Hause, H. Jim Fulford | 1999-06-01 |
| 5909622 | Asymmetrical p-channel transistor formed by nitrided oxide and large tilt angle LDD implant | Daniel Kadosh | 1999-06-01 |
| 5907780 | Incorporating silicon atoms into a metal oxide gate dielectric using gas cluster ion beam implantation | Mark C. Gilmer | 1999-05-25 |
| 5905285 | Ultra short trench transistors and process for making same | Fred N. Hause | 1999-05-18 |
| 5904517 | Ultra thin high K spacer material for use in transistor fabrication | H. Jim Fulford, Derrick J. Wristers | 1999-05-18 |
| 5904529 | Method of making an asymmetrical IGFET and providing a field dielectric between active regions of a semiconductor substrate | Daniel Kadosh | 1999-05-18 |
| 5904539 | Semiconductor trench isolation process resulting in a silicon mesa having enhanced mechanical and electrical properties | Fred N. Hause, Robert Dawson, Charles E. May, Kuang-Yeh Chang | 1999-05-18 |
| 5904542 | Performing a semiconductor fabrication sequence within a common chamber and without opening the chamber beginning with forming a field dielectric and concluding with a gate dielectric | Mark C. Gilmer, Thomas E. Spikes, Jr. | 1999-05-18 |
| 5899732 | Method of implanting silicon through a polysilicon gate for punchthrough control of a semiconductor device | Derick J. Wristers, Robert Dawson, H. Jim Fulford, Frederick N. Hause, Mark W. Michael +1 more | 1999-05-04 |
| 5900666 | Ultra-short transistor fabrication scheme for enhanced reliability | H. Jim Fulford | 1999-05-04 |
| 5899721 | Method of based spacer formation for ultra-small sapcer geometries | Derrick J. Wristers | 1999-05-04 |
| 5898202 | Selective spacer formation for optimized silicon area reduction | H. Jim Fulford | 1999-04-27 |
| 5898189 | Integrated circuit including an oxide-isolated localized substrate and a standard silicon substrate and fabrication method | Daniel Kadosh, Michael Duane | 1999-04-27 |
| 5897358 | Semiconductor device having fluorine-enhanced transistor with elevated active regions and fabrication thereof | Mark C. Gilmer, Thomas E. Spikes, Jr. | 1999-04-27 |
| 5895955 | MOS transistor employing a removable, dual layer etch stop to protect implant regions from sidewall spacer overetch | Fred N. Hause, H. Jim Fulford | 1999-04-20 |
| 5891793 | Transistor fabrication process employing a common chamber for gate oxide and gate conductor formation | Fred N. Hause | 1999-04-06 |
| 5891787 | Semiconductor fabrication employing implantation of excess atoms at the edges of a trench isolation structure | H. Jim Fulford, Derick J. Wristers | 1999-04-06 |
| 5890269 | Semiconductor wafer, handling apparatus, and method | Mark C. Gilmer | 1999-04-06 |
| 5888880 | Trench transistor with localized source/drain regions implanted through selectively grown oxide layer | H. Jim Fulford, Frederick N. Hause | 1999-03-30 |
| 5888872 | Method for forming source drain junction areas self-aligned between a sidewall spacer and an etched lateral sidewall | Daniel Kadosh | 1999-03-30 |
| 5888870 | Memory cell fabrication employing an interpoly gate dielectric arranged upon a polished floating gate | Mark C. Gilmer | 1999-03-30 |
| 5888853 | Integrated circuit including a graded grain structure for enhanced transistor formation and fabrication method thereof | Daniel Kadosh, Michael Duane | 1999-03-30 |