MG

Mark I. Gardner

AM AMD: 507 patents #1 of 9,279Top 1%
TL Tokyo Electron Limited: 92 patents #12 of 5,567Top 1%
AP Advanced Microdevices Pvt: 2 patents #1 of 26Top 4%
Infineon Technologies Ag: 2 patents #3,160 of 7,486Top 45%
📍 Prairieville, TX: #1 of 6 inventorsTop 20%
🗺 Texas: #2 of 125,132 inventorsTop 1%
Overall (All Time): #244 of 4,157,543Top 1%
608
Patents All Time

Issued Patents All Time

Showing 501–525 of 608 patents

Patent #TitleCo-InventorsDate
5888675 Reticle that compensates for radiation-induced lens error in a photolithographic system Bradley T. Moore, Robert Dawson, H. Jim Fulford, Frederick N. Hause, Mark W. Michael +1 more 1999-03-30
5885887 Method of making an igfet with selectively doped multilevel polysilicon gate Frederick N. Hause, Robert Dawson, H. Jim Fulford Jr., Mark W. Michael, Bradley T. Moore +1 more 1999-03-23
5885879 Thin polysilicon masking technique for improved lithography control Fred N. Hause 1999-03-23
5885877 Composite gate electrode incorporating dopant diffusion-retarding barrier layer adjacent to underlying gate dielectric Robert Dawson, H. Jim Fulford, Frederick N. Hause, Daniel Kadosh, Mark W. Michael +2 more 1999-03-23
5885874 Method of making enhancement-mode and depletion-mode IGFETS using selective doping of a gate material — 1999-03-23
5885861 Reduction of dopant diffusion by the co-implantation of impurities into the transistor gate conductor H. Jim Fulford, Derrick J. Wristers 1999-03-23
5885761 Semiconductor device having an elevated active region formed from a thick polysilicon layer and method of manufacture thereof Michael Duane, Daniel Kadosh 1999-03-23
5882983 Trench isolation structure partially bound between a pair of low K dielectric structures H. Jim Fulford, Charles E. May 1999-03-16
5882993 Integrated circuit with differing gate oxide thickness and process for making same Fred N. Hause 1999-03-16
5882974 High-performance PMOS transistor using a barrier implant in the source-side of the transistor channel H. Jim Fulford 1999-03-16
5882973 Method for forming an integrated circuit having transistors of dissimilarly graded junction profiles Fred N. Hause, H. Jim. Fulford, Jr. 1999-03-16
5882959 Multi-level transistor fabrication method having an inverted, upper level transistor which shares a gate conductor with a non-inverted, lower level transistor Daniel Kadosh 1999-03-16
5877057 Method of forming ultra-thin oxides with low temperature oxidation Mark C. Gilmer 1999-03-02
5877050 Method of making N-channel and P-channel devices using two tube anneals and two rapid thermal anneals Derick J. Wristers, H. Jim Fulford 1999-03-02
5877058 Method of forming an insulated-gate field-effect transistor with metal spacers Robert Dawson, H. Jim Fulford, Frederick N. Hause, Mark W. Michael, Bradley T. Moore +1 more 1999-03-02
5874343 CMOS integrated circuit and method for forming source/drain areas prior to forming lightly doped drains to optimize the thermal diffusivity thereof H. Jim Fulford, Derick J. Wristers 1999-02-23
5874341 Method of forming trench transistor with source contact in trench Daniel Kadosh, Frederick N. Hause 1999-02-23
5874340 Method for fabrication of a non-symmetrical transistor with sequentially formed gate electrode sidewalls Derick J. Wristers, H. Jim Fulford 1999-02-23
5872029 Method for forming an ultra high density inverter using a stacked transistor arrangement Daniel Kadosh 1999-02-16
5872376 Oxide formation technique using thin film silicon deposition Mark C. Gilmer 1999-02-16
5872049 Nitrogenated gate structure for improved transistor performance and method for making same H. Jim Fulford 1999-02-16
5872038 Semiconductor device having an elevated active region formed in an oxide trench and method of manufacture thereof Michael Duane, Daniel Kadosh 1999-02-16
5869379 Method of forming air gap spacer for high performance MOSFETS' Daniel Kadosh, Michael Duane 1999-02-09
5869866 Integrated circuit having sacrificial spacers for producing graded NMOS source/drain junctions possibly dissimilar from PMOS source/drain junctions H. Jim Fulford, Derick J. Wristers 1999-02-09
5869879 CMOS integrated circuit having a sacrificial metal spacer for producing graded NMOS source/drain junctions dissimilar from PMOS source/drain junctions H. Jim Fulford, Derick J. Wristers 1999-02-09