Issued Patents All Time
Showing 551–575 of 608 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5834354 | Ultra high density NOR gate using a stacked transistor arrangement | Daniel Kadosh | 1998-11-10 |
| 5831306 | Asymmetrical transistor with lightly doped drain region, heavily doped source and drain regions, and ultra-heavily doped source region | H. Jim Fulford, Derick J. Wristers | 1998-11-03 |
| 5827761 | Method of making NMOS and devices with sequentially formed gates having different gate lengths | H. Jim Fulford, Robert Dawson, Frederick N. Hause, Mark W. Michael, Bradley T. Moore +1 more | 1998-10-27 |
| 5827763 | Method of forming a multiple transistor channel doping using a dual resist fabrication sequence | Fred N. Hause | 1998-10-27 |
| 5821146 | Method of fabricating FET or CMOS transistors using MeV implantation | Kuang-Yeh Chang, Yowjuang W. Liu, Fred N. Hause | 1998-10-13 |
| 5821172 | Oxynitride GTE dielectrics using NH.sub.3 gas | Mark C. Gilmer | 1998-10-13 |
| 5818069 | Ultra high density series-connected transistors formed on separate elevational levels | Daniel Kadosh | 1998-10-06 |
| 5817560 | Ultra short trench transistors and process for making same | Fred N. Hause | 1998-10-06 |
| 5811222 | Method of selectively exposing a material using a photosensitive layer and multiple image patterns | Derick J. Wristers, H. Jim Fulford | 1998-09-22 |
| 5811347 | Nitrogenated trench liner for improved shallow trench isolation | Fred N. Hause, Kuang-Yeh Chang | 1998-09-22 |
| 5808319 | Localized semiconductor substrate for multilevel transistors | Daniel Kadosh | 1998-09-15 |
| 5804497 | Selectively doped channel region for increased I.sub.Dsat and method for making same | H. Jim Fulford, Fred N. Hause | 1998-09-08 |
| 5801075 | Method of forming trench transistor with metal spacers | Robert Dawson, H. Jim Fulford, Frederick N. Hause, Mark W. Michael, Bradley T. Moore +1 more | 1998-09-01 |
| 5801088 | Method of forming a gate electrode for an IGFET | Derick J. Wristers, H. Jim Fulford | 1998-09-01 |
| 5795809 | Semiconductor wafer fabrication process including gettering utilizing a combined oxidation technique | H. Jim Fulford, Said Ghneim | 1998-08-18 |
| 5795807 | Semiconductor device having a group of high performance transistors and method of manufacture thereof | Daniel Kadosh | 1998-08-18 |
| 5796143 | Trench transistor in combination with trench array | H. Jim Fulford, Derick J. Wristers | 1998-08-18 |
| 5793090 | Integrated circuit having multiple LDD and/or source/drain implant steps to enhance circuit performance | Fred N. Hause, H. Jim Fulford | 1998-08-11 |
| 5793089 | Graded MOS transistor junction formed by aligning a sequence of implants to a selectively removable polysilicon sidewall space and oxide thermally grown thereon | H. Jim Fulford, Fred N. Hause | 1998-08-11 |
| 5789298 | High performance mosfet structure having asymmetrical spacer formation and method of making the same | Fred N. Hause | 1998-08-04 |
| 5789787 | Asymmetrical N-channel and P-channel devices | Daniel Kadosh | 1998-08-04 |
| 5789780 | Transistor with source and drain regions within the semiconductor substrate detached or laterally displaced from the transistor gate | H. Jim Fulford | 1998-08-04 |
| 5786256 | Method of reducing MOS transistor gate beyond photolithographically patterned dimension | Fred N. Hause, H. Jim Fulford | 1998-07-28 |
| 5783469 | Method for making nitrogenated gate structure for improved transistor performance | Mark C. Gilmer | 1998-07-21 |
| 5780340 | Method of forming trench transistor and isolation trench | Daniel Kadosh, Jon D. Cheek | 1998-07-14 |