Issued Patents All Time
Showing 576–600 of 608 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5770517 | Semiconductor fabrication employing copper plug formation within a contact area | Fred N. Hause | 1998-06-23 |
| 5770485 | MOSFET device with an amorphized source and fabrication method thereof | H. Jim Fulford, Derick J. Wristers | 1998-06-23 |
| 5770483 | Multi-level transistor fabrication method with high performance drain-to-gate connection | Daniel Kadosh, Fred N. Hause | 1998-06-23 |
| 5766969 | Multiple spacer formation/removal technique for forming a graded junction | H. Jim Fulford, Derick J. Wristers | 1998-06-16 |
| 5763311 | High performance asymmetrical MOSFET structure and method of making the same | Daniel Kadosh, Fred N. Hause | 1998-06-09 |
| 5763310 | Integrated circuit employing simultaneously formed isolation and transistor trenches | — | 1998-06-09 |
| 5761481 | Semiconductor simulator tool for experimental N-channel transistor modeling | Daniel Kadoch | 1998-06-02 |
| 5759897 | Method of making an asymmetrical transistor with lightly and heavily doped drain regions and ultra-heavily doped source region | Daniel Kadosh, Robert Dawson | 1998-06-02 |
| 5756383 | Method of manufacturing an active region of a semiconductor by diffusing a counterdopant out of a sidewall spacer | — | 1998-05-26 |
| 5747367 | Multi-level transistor fabrication method with high performance source/drain connection | Daniel Kadosh | 1998-05-05 |
| 5747852 | LDD MOS transistor with improved uniformity and controllability of alignment | K.T Chang, Fred N. Hause | 1998-05-05 |
| 5723238 | Inspection of lens error associated with lens heating in a photolithographic system | Bradley T. Moore, Robert Dawson, H. Jim Fulford, Frederick N. Hause, Mark W. Michael +1 more | 1998-03-03 |
| 5719067 | Trench transistor and method for making same | Fred N. Hause | 1998-02-17 |
| 5714394 | Method of making an ultra high density NAND gate using a stacked transistor arrangement | Daniel Kadosh | 1998-02-03 |
| 5710054 | Method of forming a shallow junction by diffusion from a silicon-based spacer | Robert Dawson, H. Jim Fulford, Frederick N. Hause, Mark W. Michael, Bradley T. Moore +1 more | 1998-01-20 |
| 5693547 | Method of making vertical MOSFET with sub-trench source contact | Michael Duane | 1997-12-02 |
| 5679585 | Method for forming metal silicide on a semiconductor surface with minimal effect on pre-existing implants | Fred N. Hause, Derick J. Wristers, Dim-Lee Kwong | 1997-10-21 |
| 5677224 | Method of making asymmetrical N-channel and P-channel devices | Daniel Kadosh | 1997-10-14 |
| 5672531 | Method for fabrication of a non-symmetrical transistor | Michael Duane, Derick J. Wristers | 1997-09-30 |
| 5656518 | Method for fabrication of a non-symmetrical transistor | Daniel Kadosh, Derick J. Wristers | 1997-08-12 |
| 5654215 | Method for fabrication of a non-symmetrical transistor | Daniel Kadosh, Robert Dawson | 1997-08-05 |
| 5648286 | Method of making asymmetrical transistor with lightly doped drain region, heavily doped source and drain regions, and ultra-heavily doped source region | H. Jim Fulford, Derick J. Wristers | 1997-07-15 |
| 5643825 | Integrated circuit isolation process | Fred N. Hause, Kuang-Yeh Chang | 1997-07-01 |
| 5554562 | Advanced isolation scheme for deep submicron technology | Kuang-Yeh Chang, Yowjuang W. Liu, Frederick N. Hause | 1996-09-10 |
| 5538923 | Method for achieving a high quality thin oxide using a sacrificial oxide anneal | Henry Jim Fulford | 1996-07-23 |