Issued Patents All Time
Showing 526–550 of 608 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5866934 | Parallel and series-coupled transistors having gate conductors formed on sidewall surfaces of a sacrificial structure | Daniel Kadosh, Jon D. Cheek | 1999-02-02 |
| 5863824 | Method of forming semiconductor devices using gate electrode length and spacer width for controlling drivecurrent strength | Jim Fulford, Anthony J. Toprac | 1999-01-26 |
| 5861335 | Semiconductor fabrication employing a post-implant anneal within a low temperature high pressure nitrogen ambient to improve channel and gate oxide reliability | Fred N. Hause | 1999-01-19 |
| 5858848 | Semiconductor fabrication employing self-aligned sidewall spacers laterally adjacent to a transistor gate | Mark C. Gilmer | 1999-01-12 |
| 5854121 | Semiconductor fabrication employing barrier atoms incorporated at the edges of a trench isolation structure | H. Jim Fulford, Derick J. Wristers | 1998-12-29 |
| 5854115 | Formation of an etch stop layer within a transistor gate conductor to provide for reduction of channel length | Daniel Kadosh, Michael Duane | 1998-12-29 |
| 5851921 | Semiconductor device and method for forming the device using a dual layer, self-aligned silicide to enhance contact performance | Fred N. Hause | 1998-12-22 |
| 5851307 | Method for in-situ cleaning of polysilicon-coated quartz furnaces | Mark C. Gilmer, Robert Paiz | 1998-12-22 |
| 5851883 | High density integrated circuit process | Daniel Kadosh, Fred N. Hause | 1998-12-22 |
| 5851888 | Controlled oxide growth and highly selective etchback technique for forming ultra-thin oxide | Mark C. Gilmer | 1998-12-22 |
| 5851891 | IGFET method of forming with silicide contact on ultra-thin gate | Robert Dawson, H. Jim Fulford, Frederick N. Hause, Mark W. Michael, Bradley T. Moore +1 more | 1998-12-22 |
| 5851893 | Method of making transistor having a gate dielectric which is substantially resistant to drain-side hot carrier injection | H. Jim Fulford | 1998-12-22 |
| 5851901 | Method of manufacturing an isolation region of a semiconductor device with advanced planarization | Mark C. Gilmer | 1998-12-22 |
| 5849622 | Method of forming a source implant at a contact masking step of a process flow | Frederick N. Hause | 1998-12-15 |
| 5849621 | Method and structure for isolating semiconductor devices after transistor formation | Fred N. Hause, H. Jim Fulford | 1998-12-15 |
| 5849643 | Gate oxidation technique for deep sub quarter micron transistors | Mark C. Gilmer, Daniel Kadosh | 1998-12-15 |
| 5847428 | Integrated circuit gate conductor which uses layered spacers to produce a graded junction | H. Jim Fulford, Derick J. Wristers | 1998-12-08 |
| 5843625 | Method of reducing via and contact dimensions beyond photolithography equipment limits | Fred N. Hause, Robert Dawson | 1998-12-01 |
| 5844276 | CMOS integrated circuit and method for implanting NMOS transistor areas prior to implanting PMOS transistor areas to optimize the thermal diffusivity thereof | H. Jim Fulford, Derick J. Wristers | 1998-12-01 |
| 5841168 | High performance asymmetrical MOSFET structure and method of making the same | Fred N. Hause, Daniel Kadosh | 1998-11-24 |
| 5840451 | Individually controllable radiation sources for providing an image pattern in a photolithographic system | Bradley T. Moore, Robert Dawson, H. Jim Fulford, Frederick N. Hause, Mark W. Michael +1 more | 1998-11-24 |
| 5840610 | Enhanced oxynitride gate dielectrics using NF.sub.3 gas | Mark C. Gilmer | 1998-11-24 |
| 5837572 | CMOS integrated circuit formed by using removable spacers to produce asymmetrical NMOS junctions before asymmetrical PMOS junctions for optimizing thermal diffusivity of dopants implanted therein | Fred N. Hause, H. Jim Fulford | 1998-11-17 |
| 5837557 | Semiconductor fabrication method of forming a master layer to combine individually printed blocks of a circuit pattern | H. Jim Fulford, Robert Dawson, Frederick N. Hause, Mark W. Michael, Bradley T. Moore +1 more | 1998-11-17 |
| 5834350 | Elevated transistor fabrication technique | Daniel Kadosh, Michael Duane | 1998-11-10 |