Issued Patents All Time
Showing 376–400 of 608 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6017802 | Ultra-short transistor fabrication scheme for enhanced reliability | H. Jim Fulford | 2000-01-25 |
| 6018179 | Transistors having a scaled channel length and integrated spacers with enhanced silicidation properties | Fred N. Hause, Derick J. Wristers | 2000-01-25 |
| 6015739 | Method of making gate dielectric for sub-half micron MOS transistors including a graded dielectric constant | H. Jim Fulford, Dim-Lee Kwong | 2000-01-18 |
| 6013546 | Semiconductor device having a PMOS device with a source/drain region formed using a heavy atom p-type implant and method of manufacture thereof | H. Jim Fulford, Jack Lee | 2000-01-11 |
| 6011290 | Short channel length MOSFET transistor | H. Jim Fulford | 2000-01-04 |
| 6010957 | Semiconductor device having tapered conductive lines and fabrication thereof | Daniel Kadosh | 2000-01-04 |
| 6008521 | Integrated circuit employing simultaneously formed isolation and transistor trenches | — | 1999-12-28 |
| 6008109 | Trench isolation structure having a low K dielectric encapsulated by oxide | H. Jim Fulford, Charles E. May | 1999-12-28 |
| 6008096 | Ultra short transistor fabrication method | Michael Duane, Daniel Kadosh | 1999-12-28 |
| 6008095 | Process for formation of isolation trenches with high-K gate dielectrics | H. Jim Fulford, Charles E. May | 1999-12-28 |
| 6005285 | Argon doped epitaxial layers for inhibiting punchthrough within a semiconductor device | H. Jim Fulford, Charles E. May | 1999-12-21 |
| 6005274 | Semiconductor device with a multi-level gate structure and a gate dielectric composed of barium zirconium titanate material | Mark C. Gilmer | 1999-12-21 |
| 6005272 | Trench transistor with source contact in trench | Daniel Kadosh, Frederick N. Hause | 1999-12-21 |
| 6004861 | Process for making a discontinuous source/drain formation for a high density integrated circuit | Mark C. Gilmer | 1999-12-21 |
| 6004849 | Method of making an asymmetrical IGFET with a silicide contact on the drain without a silicide contact on the source | Daniel Kadosh, Michael Duane | 1999-12-21 |
| 6002150 | Compound material T gate structure for devices with gate dielectrics having a high dielectric constant | Mark C. Gilmer | 1999-12-14 |
| 5998288 | Ultra thin spacers formed laterally adjacent a gate conductor recessed below the upper surface of a substrate | H. Jim Fulford | 1999-12-07 |
| 5998270 | Formation of oxynitride and polysilicon layers in a single reaction chamber | Mark C. Gilmer | 1999-12-07 |
| 5994779 | Semiconductor fabrication employing a spacer metallization technique | Daniel Kadosh, Fred N. Hause | 1999-11-30 |
| 5994193 | Method of making high performance MOSFET with integrated poly/metal gate electrode | Derick J. Wristers, Jon D. Cheek | 1999-11-30 |
| 5994175 | High performance MOSFET with low resistance design | H. Jim Fulford, Derick J. Wristers | 1999-11-30 |
| 5990532 | Semiconductor arrangement with lightly doped regions under a gate structure | — | 1999-11-23 |
| 5990493 | Diamond etch stop rendered conductive by a gas cluster ion beam implant of titanium | Mark C. Gilmer | 1999-11-23 |
| 5989967 | Transistor with ultra short length defined partially by sidewall oxidation of a gate conductor overlying the channel length | Mark C. Gilmer | 1999-11-23 |
| 5989964 | Post-spacer LDD implant for shallow LDD transistor | Fred N. Hause | 1999-11-23 |