Issued Patents All Time
Showing 301–325 of 608 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6090676 | Process for making high performance MOSFET with scaled gate electrode thickness | H. Jim Fulford, Charles E. May | 2000-07-18 |
| 6090694 | Local interconnect patterning and contact formation | Fred N. Hause, Charles E. May | 2000-07-18 |
| 6091105 | Method of making a self-aligned dopant enhanced RTA MOSFET | H. Jim Fulford | 2000-07-18 |
| 6086976 | Semiconductor wafer, handling apparatus, and method | Mark C. Gilmer | 2000-07-11 |
| 6087706 | Compact transistor structure with adjacent trench isolation and source/drain regions implanted vertically into trench walls | Robert Dawson, Frederick N. Hause, H. Jim Fulford, Mark W. Michael, Bradley T. Moore +1 more | 2000-07-11 |
| 6087705 | Trench isolation structure partially bound between a pair of low K dielectric structures | H. Jim Fulford, Charles E. May | 2000-07-11 |
| 6087249 | Transistor fabrication process employing a common chamber for gate oxide and gate conductor formation | Fred N. Hause | 2000-07-11 |
| 6087238 | Semiconductor device having reduced-width polysilicon gate and non-oxidizing barrier layer and method of manufacture thereof | H. Jim Fulford | 2000-07-11 |
| 6084280 | Transistor having a metal silicide self-aligned to the gate | Frederick N. Hause, Charles E. May | 2000-07-04 |
| 6083778 | Localized semiconductor substrate for multilevel for transistors | Daniel Kadosh | 2000-07-04 |
| 6083846 | Graded MOS transistor junction formed by aligning a sequence of implants to a selectively removable polysilicon sidewall space and oxide thermally grown thereon | H. Jim Fulford, Fred N. Hause | 2000-07-04 |
| 6080629 | Ion implantation into a gate electrode layer using an implant profile displacement layer | Robert Dawson, H. Jim Fulford, Frederick N. Hause, Mark W. Michael, Bradley T. Moore +1 more | 2000-06-27 |
| 6080640 | Metal attachment method and structure for attaching substrates at low temperatures | Fred N. Hause, Daniel Kadosh | 2000-06-27 |
| 6080676 | Device and method for etching spacers formed upon an integrated circuit gate conductor | Thien T. Nguyen, Charles E. May | 2000-06-27 |
| 6078080 | Asymmetrical transistor with lightly and heavily doped drain regions and ultra-heavily doped source region | Daniel Kadosh, Robert Dawson | 2000-06-20 |
| 6078078 | V-gate transistor | H. Jim Fulford, Charles E. May | 2000-06-20 |
| 6078089 | Semiconductor device having cobalt niobate-metal silicide electrode structure and process of fabrication thereof | Mark C. Gilmer | 2000-06-20 |
| 6077749 | Method of making dual channel gate oxide thickness for MOSFET transistor design | H. Jim Fulford, Charles E. May | 2000-06-20 |
| 6077748 | Advanced trench isolation fabrication scheme for precision polysilicon gate control | Daniel Kadosh, Michael Duane | 2000-06-20 |
| 6075268 | Ultra high density inverter using a stacked transistor arrangement | Daniel Kadosh | 2000-06-13 |
| 6074904 | Method and structure for isolating semiconductor devices after transistor formation | Thomas E. Spikes, Jr., Mark W. Michael, Robert Dawson | 2000-06-13 |
| 6074919 | Method of forming an ultrathin gate dielectric | Thien T. Nguyen | 2000-06-13 |
| 6075258 | Elevated transistor fabrication technique | Daniel Kadosh, Michael Duane | 2000-06-13 |
| 6072192 | Test structure responsive to electrical signals for determining lithographic misalignment of vias relative to electrically active elements | H. Jim Fulford, Fred N. Hause | 2000-06-06 |
| 6072213 | Transistor having an etchant-scalable channel length and method of making same | Mark C. Gilmer | 2000-06-06 |