Issued Patents All Time
Showing 426–450 of 634 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6764884 | Method for forming a gate in a FinFET device and thinning a fin in a channel region of the FinFET device | Haihong Wang | 2004-07-20 |
| 6765227 | Semiconductor-on-insulator (SOI) wafer having a Si/SiGe/Si active layer and method of fabrication using wafer bonding | William G. En, Judy Xilin An, Concetta Riccobene | 2004-07-20 |
| 6764908 | Narrow width CMOS devices fabricated on strained lattice semiconductor substrates with maximized NMOS and PMOS drive currents | Daniel Kadosh, Derick J. Wristers, Qi Xiang | 2004-07-20 |
| 6762448 | FinFET device with multiple fin structures | Ming-Ren Lin, Haihong Wang | 2004-07-13 |
| 6762483 | Narrow fin FinFET | Zoran Krivokapic, Judy Xilin An, Srikanteswara Dakshina-Murthy, Haihong Wang | 2004-07-13 |
| 6756643 | Dual silicon layer for chemical mechanical polishing planarization | Krishnashree Achuthan, Shibly S. Ahmed, Haihong Wang | 2004-06-29 |
| 6756277 | Replacement gate process for transistors having elevated source and drain regions | — | 2004-06-29 |
| 6753182 | Cryopreservation of plant cells | Prakash G. Kadkade, Christopher B. Bare, Barbara Schnabel-Preikstas | 2004-06-22 |
| 6746926 | MOS transistor with highly localized super halo implant | — | 2004-06-08 |
| 6746944 | Low nisi/si interface contact resistance with preamorphizing and laser thermal annealing | Qi Xiang, Robert B. Ogle, Eric N. Paton, Cyrus E. Tabery | 2004-06-08 |
| 6743687 | Abrupt source/drain extensions for CMOS transistors | — | 2004-06-01 |
| 6743689 | Method of fabrication SOI devices with accurately defined monocrystalline source/drain extensions | Eric N. Paton, Robert B. Ogle, Cyrus E. Tabery, Qi Xiang | 2004-06-01 |
| 6743680 | Process for manufacturing transistors having silicon/germanium channel regions | — | 2004-06-01 |
| 6716690 | Uniformly doped source/drain junction in a double-gate MOSFET | Haihong Wang, Judy Xilin An | 2004-04-06 |
| 6716686 | Method for forming channels in a finfet device | Matthew S. Buynoski, Judy Xilin An | 2004-04-06 |
| 6717212 | Leaky, thermally conductive insulator material (LTCIM) in semiconductor-on-insulator (SOI) structure | Dong-Hyuk Ju, William G. En, Srinath Krishnan, Concetta Riccobene, Zoran Krivokapic +1 more | 2004-04-06 |
| 6709935 | Method of locally forming a silicon/geranium channel layer | — | 2004-03-23 |
| 6709982 | Double spacer FinFET formation | Matthew S. Buynoski, Judy Xilin An, Haihong Wang | 2004-03-23 |
| 6706614 | Silicon-on-insulator (SOI) transistor having partial hetero source/drain junctions fabricated with high energy germanium implantation. | Judy Xilin An | 2004-03-16 |
| 6706571 | Method for forming multiple structures in a semiconductor device | Judy Xilin An, Cyrus E. Tabery, Haihong Wang | 2004-03-16 |
| 6703277 | Reducing agent for high-K gate dielectric parasitic interfacial layer | Eric N. Paton | 2004-03-09 |
| 6703281 | Differential laser thermal process with disposable spacers | — | 2004-03-09 |
| 6696725 | Dual-gate MOSFET with channel potential engineering | Judy Xilin An | 2004-02-24 |
| 6693333 | Semiconductor-on-insulator circuit with multiple work functions | — | 2004-02-17 |
| 6689671 | Low temperature solid-phase epitaxy fabrication process for MOS devices built on strained semiconductor substrate | Derick J. Wristers | 2004-02-10 |