Issued Patents All Time
Showing 401–425 of 634 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6853020 | Double-gate semiconductor device | Judy Xilin An | 2005-02-08 |
| 6852576 | Method for forming structures in finfet devices | Ming-Ren Lin, Haihong Wang | 2005-02-08 |
| 6835618 | Epitaxially grown fin for FinFET | Srikanteswara Dakshina-Murthy, Chih-Yuh Yang | 2004-12-28 |
| 6833588 | Semiconductor device having a U-shaped gate structure | Shibly S. Ahmed, Judy Xilin An, Srikanteswara Dakshina-Murthy, Zoran Krivokapic, Haihong Wang | 2004-12-21 |
| 6827840 | Chiral ligand exchange potentiometry and enantioselective sensors | Kalle Levon, Yanxiu Zhou | 2004-12-07 |
| 6825115 | Post silicide laser thermal annealing to avoid dopant deactivation | Qi Xiang, Robert B. Ogle, Eric N. Paton, Cyrus E. Tabery | 2004-11-30 |
| 6815268 | Method for forming a gate in a FinFET device | Judy Xilin An, Srikanteswara Dakshina-Murthy | 2004-11-09 |
| 6812076 | Dual silicon layer for chemical mechanical polishing planarization | Krishnashree Achuthan, Shibly S. Ahmed, Haihong Wang | 2004-11-02 |
| 6812106 | Reduced dopant deactivation of source/drain extensions using laser thermal annealing | Qi Xiang, Robert B. Ogle, Eric N. Paton, Cyrus E. Tabery | 2004-11-02 |
| 6812119 | Narrow fins by oxidation in double-gate finfet | Shibly S. Ahmed, Ming-Ren Lin, Haihong Wang | 2004-11-02 |
| 6806147 | Method and apparatus for suppressing the channeling effect in high energy deep well implantation | Che-Hoo Ng | 2004-10-19 |
| 6803631 | Strained channel finfet | Srikanteswara Dakshina-Murthy, Judy Xilin An, Zoran Krivokapic, Haihong Wang | 2004-10-12 |
| 6800885 | Asymmetrical double gate or all-around gate MOSFET devices and methods for making same | Judy Xilin An | 2004-10-05 |
| RE38608 | Low-voltage punch-through transient suppressor employing a dual-base structure | Chenming Hu, Ya-Chin King, Jeffrey T. Pohlman, Rita Trivedi | 2004-10-05 |
| 6787402 | Double-gate vertical MOSFET transistor and fabrication method | — | 2004-09-07 |
| 6787424 | Fully depleted SOI transistor with elevated source and drain | — | 2004-09-07 |
| 6787439 | Method using planarizing gate material to improve gate critical dimension in semiconductor devices | Shibly S. Ahmed, Cyrus E. Tabery, Haihong Wang | 2004-09-07 |
| 6787476 | Etch stop layer for etching FinFET gate over a large topography | Srikanteswara Dakshina-Murthy, Cyrus E. Tabery, Chih-Yuh Yang | 2004-09-07 |
| 6787852 | Semiconductor-on-insulator (SOI) device having source/drain silicon-germanium regions | Ralf van Bentum | 2004-09-07 |
| 6787854 | Method for forming a fin in a finFET device | Chih-Yuh Yang, Shibly S. Ahmed, Srikanteswara Dakshina-Murthy, Cyrus E. Tabery, Haihong Wang | 2004-09-07 |
| 6787406 | Systems and methods for forming dense n-channel and p-channel fins using shadow implanting | Wiley Eugene Hill, Shibly S. Ahmed, Haihong Wang | 2004-09-07 |
| 6785240 | Method for estimating the traffic matrix of a communication network | Jin Cao, R. Drew Davis, Scott Alan Vander Wiel | 2004-08-31 |
| 6784101 | Formation of high-k gate dielectric layers for MOS devices fabricated on strained lattice semiconductor substrates with minimized stress relaxation | David Wu | 2004-08-31 |
| 6780789 | Laser thermal oxidation to form ultra-thin gate oxide | Robert B. Ogle, Eric N. Paton, Cyrus E. Tabery, Qi Xiang | 2004-08-24 |
| 6774436 | SOI MOSFET with asymmetrical source/body and drain/body junctions | Ralf van Bentum | 2004-08-10 |