Issued Patents All Time
Showing 351–375 of 634 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7196374 | Doped structure for FinFET devices | Ming-Ren Lin | 2007-03-27 |
| 7186599 | Narrow-body damascene tri-gate FinFET | Shibly S. Ahmed, Haihong Wang | 2007-03-06 |
| 7183152 | Epitaxially grown fin for FinFET | Srikanteswara Dakshina-Murthy, Chih-Yuh Yang | 2007-02-27 |
| 7183223 | Methods for forming small contacts | Cyrus E. Tabery, Srikanteswara Dakshina-Murthy, Chih-Yuh Yang | 2007-02-27 |
| 7179692 | Method of manufacturing a semiconductor device having a fin structure | Shibly S. Ahmed, Judy Xilin An, Srikanteswara Dakshina-Murthy, Zoran Krivokapic, Haihong Wang | 2007-02-20 |
| 7148526 | Germanium MOSFET devices and methods for making same | Judy Xilin An, Zoran Krivokapic, Haihong Wang | 2006-12-12 |
| 7125776 | Multi-step chemical mechanical polishing of a gate area in a FinFET | Krishnashree Achuthan, Shibly S. Ahmed, Haihong Wang | 2006-10-24 |
| 7112847 | Smooth fin topology in a FinFET device | Haihong Wang | 2006-09-26 |
| 7099798 | Event-based system and process for recording and playback of collaborative electronic presentations | Yong Rui | 2006-08-29 |
| 7095065 | Varying carrier mobility in semiconductor devices to achieve overall design goals | Shibly S. Ahmed, Haihong Wang | 2006-08-22 |
| 7091068 | Planarizing sacrificial oxide to improve gate critical dimension in semiconductor devices | Shibly S. Ahmed, Cyrus E. Tabery | 2006-08-15 |
| 7091097 | End-of-range defect minimization in semiconductor device | Eric N. Paton, Qi Xiang, Cyrus E. Tabery, Robert B. Ogle | 2006-08-15 |
| 7084018 | Sacrificial oxide for minimizing box undercut in damascene FinFET | Shibly S. Ahmed | 2006-08-01 |
| 7064022 | Method of forming merged FET inverter/logic gate | Wiley Eugene Hill, Ming-Ren Lin | 2006-06-20 |
| 7041542 | Damascene tri-gate FinFET | Shibly S. Ahmed, Haihong Wang | 2006-05-09 |
| 7041601 | Method of manufacturing metal gate MOSFET with strained channel | Haihong Wang | 2006-05-09 |
| 7034361 | Narrow body raised source/drain metal gate MOSFET | Shibly S. Ahmed, Haihong Wang | 2006-04-25 |
| 7029958 | Self aligned damascene gate | Cyrus E. Tabery, Shibly S. Ahmed, Matthew S. Buynoski, Srikanteswara Dakshina-Murthy, Zoran Krivokapic +2 more | 2006-04-18 |
| 7029959 | Source and drain protection and stringer-free gate formation in semiconductor devices | Chih-Yuh Yang, Shibly S. Ahmed, Srikanteswara Dakshina-Murhty, Cyrus E. Tabery | 2006-04-18 |
| 7019363 | MOS transistor with asymmetrical source/drain extensions | — | 2006-03-28 |
| 6998301 | Method for forming a tri-gate MOSFET | Shibly S. Ahmed | 2006-02-14 |
| 6995438 | Semiconductor device with fully silicided source/drain and damascence metal gate | Shibly S. Ahmed, Haihong Wang | 2006-02-07 |
| 6984569 | Shallow trench isolation (STI) region with high-K liner and method of formation | Olov Karlsson, Haihong Wang, Zoran Krivokapic, Qi Xiang | 2006-01-10 |
| 6982464 | Dual silicon layer for chemical mechanical polishing planarization | Krishnashree Achuthan, Shibly S. Ahmed, Haihong Wang | 2006-01-03 |
| 6979635 | Method of forming miniaturized polycrystalline silicon gate electrodes using selective oxidation | Akif Sultan, Qi Xiang | 2005-12-27 |