Issued Patents All Time
Showing 451–475 of 634 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6686231 | Damascene gate process with sacrificial oxide in semiconductor devices | Shibly S. Ahmed, Haihong Wang | 2004-02-03 |
| 6686248 | Method of fabricating a semiconductor device having a MOS transistor with a high dielectric constant material | — | 2004-02-03 |
| 6682973 | Formation of well-controlled thin SiO, SiN, SiON layer for multilayer high-K dielectric applications | Eric N. Paton, Qi Xiang | 2004-01-27 |
| 6680233 | Semiconductor device formed with disposable spacer and liner using high-K material and method of fabrication | Qi Xiang, Haihong Wang | 2004-01-20 |
| 6680250 | Formation of deep amorphous region to separate junction from end-of-range defects | Eric N. Paton, Robert B. Ogle, Cyrus E. Tabery, Qi Xiang | 2004-01-20 |
| 6670260 | Transistor with local insulator structure | Ming-Ren Lin, Shekhar Pramanick | 2003-12-30 |
| 6664146 | Integration of fully depleted and partially depleted field effect transistors formed in SOI technology | — | 2003-12-16 |
| 6660578 | High-K dielectric having barrier layer for P-doped devices and method of fabrication | Olov Karlsson, Qi Xiang, Haihong Wang, Zoran Krivokapic | 2003-12-09 |
| 6657267 | Semiconductor device and fabrication technique using a high-K liner for spacer etch stop | Qi Xiang, Olov Karlsson, Haihong Wang | 2003-12-02 |
| 6657276 | Shallow trench isolation (STI) region with high-K liner and method of formation | Olov Karlsson, Haihong Wang, Zoran Krivokapic, Qi Xiang | 2003-12-02 |
| 6656749 | In-situ monitoring during laser thermal annealing | Eric N. Paton, Robert B. Ogle, Cyrus E. Tabery, Qi Xiang | 2003-12-02 |
| 6646307 | MOSFET having a double gate | Eric N. Paton | 2003-11-11 |
| 6645797 | Method for forming fins in a FinFET device using sacrificial carbon layer | Matthew S. Buynoski, Srikanteswara Dakshina-Murthy, Cyrus E. Tabery, Haihong Wang, Chih-Yuh Yang | 2003-11-11 |
| 6642122 | Dual laser anneal for graded halo profile | — | 2003-11-04 |
| 6630385 | MOSFET with differential halo implant and annealing strategy | — | 2003-10-07 |
| 6630712 | Transistor with dynamic source/drain extensions | — | 2003-10-07 |
| 6630386 | CMOS manufacturing process with self-amorphized source/drain junctions and extensions | — | 2003-10-07 |
| 6611029 | Double gate semiconductor device having separate gates | Shibly S. Ahmed, Haihong Wang | 2003-08-26 |
| 6566213 | Method of fabricating multi-thickness silicide device formed by disposable spacers | William G. En, Srinath Krishnan, Dong-Hyuk Ju | 2003-05-20 |
| 6566212 | Method of fabricating an integrated circuit with ultra-shallow source/drain extensions | Ming-Ren Lin | 2003-05-20 |
| 6562665 | Fabrication of a field effect transistor with a recess in a semiconductor pillar in SOI technology | — | 2003-05-13 |
| 6559015 | Fabrication of field effect transistor with dual laser thermal anneal processes | — | 2003-05-06 |
| 6555439 | Partial recrystallization of source/drain region before laser thermal annealing | Qi Xiang, Robert B. Ogle, Eric N. Paton, Cyrus E. Tabery | 2003-04-29 |
| 6555879 | SOI device with metal source/drain and method of fabrication | Zoran Krivokapic, Qi Xiang | 2003-04-29 |
| 6555437 | Multiple halo implant in a MOSFET with raised source/drain structure | — | 2003-04-29 |