Issued Patents All Time
Showing 476–500 of 634 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6551886 | Ultra-thin body SOI MOSFET and gate-last fabrication method | — | 2003-04-22 |
| 6552377 | Mos transistor with dual metal gate structure | — | 2003-04-22 |
| 6551888 | Tuning absorption levels during laser thermal annealing | Cyrus E. Tabery, Eric N. Paton, Qi Xiang, Robert B. Ogle | 2003-04-22 |
| 6551885 | Low temperature process for a thin film transistor | — | 2003-04-22 |
| 6534373 | MOS transistor with reduced floating body effect | — | 2003-03-18 |
| 6531710 | SOI film formed by laser annealing | — | 2003-03-11 |
| 6531368 | Method of fabricating a semiconductor device having a metal oxide high-k gate insulator by localized laser irradiation and a device thereby formed | — | 2003-03-11 |
| 6528858 | MOSFETs with differing gate dielectrics and method of formation | Qi Xiang, Olov Karlsson, Haihong Wang, Zoran Krivokapic | 2003-03-04 |
| 6528851 | Post-silicidation implant for introducing recombination center in body of SOI MOSFET | — | 2003-03-04 |
| 6524920 | Low temperature process for a transistor with elevated source and drain | — | 2003-02-25 |
| 6521501 | Method of forming a CMOS transistor having ultra shallow source and drain regions | Jeff P. Erhardt, G. Jonathan Kluth | 2003-02-18 |
| 6521502 | Solid phase epitaxy activation process for source/drain junction extensions and halo regions | — | 2003-02-18 |
| 6518631 | Multi-Thickness silicide device formed by succesive spacers | William G. En, Srinath Krishnan, Dong-Hyuk Ju | 2003-02-11 |
| 6514829 | Method of fabricating abrupt source/drain junctions | — | 2003-02-04 |
| 6509253 | T-shaped gate electrode for reduced resistance | — | 2003-01-21 |
| 6506650 | Method of fabrication based on solid-phase epitaxy for a MOSFET transistor with a controlled dopant profile | — | 2003-01-14 |
| 6507078 | Fabrication of a wide metal silicide on a narrow polysilicon gate structure | — | 2003-01-14 |
| 6506638 | Vertical double gate transistor structure | — | 2003-01-14 |
| 6503817 | Method for establishing dopant profile to suppress silicidation retardation effect in CMOS process | — | 2003-01-07 |
| 6504214 | MOSFET device having high-K dielectric layer | Qi Xiang | 2003-01-07 |
| 6495437 | Low temperature process to locally form high-k gate dielectrics | — | 2002-12-17 |
| 6495402 | Semiconductor-on-insulator (SOI) device having source/drain silicon-germanium regions and method of manufacture | Ralf van Bentum | 2002-12-17 |
| 6492670 | Locally confined deep pocket process for ULSI MOSFETS | — | 2002-12-10 |
| 6482705 | Method of fabricating a semiconductor device having a MOSFET with an amorphous SiGe gate electrode and an elevated crystalline SiGe source/drain structure and a device thereby formed | — | 2002-11-19 |
| 6479868 | Silicon-on-insulator transistors with asymmetric source/drain junctions formed by angled germanium implantation | Xilin Judy An, Concetta Riccobene | 2002-11-12 |