Issued Patents All Time
Showing 526–550 of 634 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6426259 | Vertical field effect transistor with metal oxide as sidewall gate insulator | — | 2002-07-30 |
| 6423599 | Method for fabricating a field effect transistor having dual gates in SOI (semiconductor on insulator) technology | — | 2002-07-23 |
| 6423647 | Formation of dielectric regions of different thicknesses at selective location areas during laser thermal processes | — | 2002-07-23 |
| 6420218 | Ultra-thin-body SOI MOS transistors having recessed source and drain regions | — | 2002-07-16 |
| 6420767 | Capacitively coupled DTMOS on SOI | Srinath Krishnan, John C. Holst | 2002-07-16 |
| 6413829 | Field effect transistor in SOI technology with schottky-contact extensions | — | 2002-07-02 |
| 6414355 | Silicon-on-insulator (SOI) chip having an active layer of non-uniform thickness | Judy Xilin An, William G. En | 2002-07-02 |
| 6410371 | Method of fabrication of semiconductor-on-insulator (SOI) wafer having a Si/SiGe/Si active layer | William G. En, Judy Xilin An, Concetta Riccobene | 2002-06-25 |
| 6406986 | Fabrication of a wide metal silicide on a narrow polysilicon gate structure | — | 2002-06-18 |
| 6406951 | Fabrication of fully depleted field effect transistor with raised source and drain in SOI technology | — | 2002-06-18 |
| 6403434 | Process for manufacturing MOS transistors having elevated source and drain regions and a high-k gate dielectric | — | 2002-06-11 |
| 6403981 | Double gate transistor having a silicon/germanium channel region | — | 2002-06-11 |
| 6403433 | Source/drain doping technique for ultra-thin-body SOI MOS transistors | Jonathan Kluth, Emi Ishida | 2002-06-11 |
| 6399469 | Fabrication of a notched gate structure for a field effect transistor using a single patterning and etch process | — | 2002-06-04 |
| 6399450 | Low thermal budget process for manufacturing MOS transistors having elevated source and drain regions | — | 2002-06-04 |
| 6399427 | Formation of ultra-thin active device area on semiconductor on insulator (SOI) substrate | — | 2002-06-04 |
| 6395609 | Method for fabricating a bipolar junction transistor with tunneling current through the gate of a field effect transistor as base current | — | 2002-05-28 |
| 6395589 | Fabrication of fully depleted field effect transistor with high-K gate dielectric in SOI technology | — | 2002-05-28 |
| 6391753 | Process for forming gate conductors | — | 2002-05-21 |
| 6391782 | Process for forming multiple active lines and gate-all-around MOSFET | — | 2002-05-21 |
| 6391728 | Method of forming a highly localized halo profile to prevent punch-through | — | 2002-05-21 |
| 6391695 | Double-gate transistor formed in a thermal process | — | 2002-05-21 |
| 6383904 | Fabrication of self-aligned front gate and back gate of a field effect transistor in semiconductor on insulator | — | 2002-05-07 |
| 6380590 | SOI chip having multiple threshold voltage MOSFETs by using multiple channel materials and method of fabricating same | — | 2002-04-30 |
| 6380019 | Method of manufacturing a transistor with local insulator structure | Ming-Ren Lin, Shekhar Pramanick | 2002-04-30 |