Issued Patents All Time
Showing 576–600 of 634 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6312995 | "MOS transistor with assisted-gates and ultra-shallow ""Psuedo"" source and drain extensions for ultra-large-scale integration" | — | 2001-11-06 |
| 6300182 | Field effect transistor having dual gates with asymmetrical doping for reduced threshold voltage | — | 2001-10-09 |
| 6297115 | Cmos processs with low thermal budget | — | 2001-10-02 |
| 6297117 | Formation of confined halo regions in field effect transistor | — | 2001-10-02 |
| 6291302 | Selective laser anneal process using highly reflective aluminum mask | — | 2001-09-18 |
| 6287925 | Formation of highly conductive junctions by rapid thermal anneal and laser thermal process | — | 2001-09-11 |
| 6284582 | MOS-gate tunneling-injection bipolar transistor | — | 2001-09-04 |
| 6284672 | Method of forming a super-shallow amorphous layer in silicon | — | 2001-09-04 |
| 6284630 | Method for fabrication of abrupt drain and source extensions for a field effect transistor | — | 2001-09-04 |
| 6281555 | Integrated circuit having isolation structures | Ming-Ren Lin | 2001-08-28 |
| 6281559 | Gate stack structure for variable threshold voltage | Ercan Adem | 2001-08-28 |
| 6274469 | Process using a plug as a mask for a gate | — | 2001-08-14 |
| 6271095 | Locally confined deep pocket process for ULSI mosfets | — | 2001-08-07 |
| 6271563 | MOS transistor with high-K spacer designed for ultra-large-scale integration | Ming-Ren Lin | 2001-08-07 |
| 6268253 | Forming a removable spacer of uniform width on sidewalls of a gate of a field effect transistor during a differential rapid thermal anneal process | — | 2001-07-31 |
| 6265250 | Method for forming SOI film by laser annealing | — | 2001-07-24 |
| 6265256 | MOS transistor with minimal overlap between gate and source/drain extensions | Judy Xilin An, Yowjuang W. Liu | 2001-07-24 |
| 6265291 | Circuit fabrication method which optimizes source/drain contact resistance | Emi Ishida | 2001-07-24 |
| 6265293 | CMOS transistors fabricated in optimized RTA scheme | — | 2001-07-24 |
| 6262456 | Integrated circuit having transistors with different threshold voltages | Ming-Ren Lin | 2001-07-17 |
| 6255175 | Fabrication of a field effect transistor with minimized parasitic Miller capacitance | — | 2001-07-03 |
| 6255174 | Mos transistor with dual pocket implant | — | 2001-07-03 |
| 6251757 | Formation of highly activated shallow abrupt junction by thermal budget engineering | — | 2001-06-26 |
| 6248637 | Process for manufacturing MOS Transistors having elevated source and drain regions | — | 2001-06-19 |
| 6245618 | Mosfet with localized amorphous region with retrograde implantation | Judy Xilin An | 2001-06-12 |