Issued Patents All Time
Showing 601–625 of 634 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6246103 | Bipolar junction transistor with tunneling current through the gate of a field effect transistor as base current | — | 2001-06-12 |
| 6235599 | Fabrication of a shallow doped junction having low sheet resistance using multiple implantations | — | 2001-05-22 |
| 6228721 | Fabrication of metal oxide structures with different thicknesses on a semiconductor substrate | — | 2001-05-08 |
| 6225661 | MOS transistor with stepped gate insulator | Judy Xilin An, Ming-Ren Lin | 2001-05-01 |
| 6225173 | Recessed channel structure for manufacturing shallow source/drain extensions | — | 2001-05-01 |
| 6225176 | Step drain and source junction formation | — | 2001-05-01 |
| 6221724 | Method of fabricating an integrated circuit having punch-through suppression | Shekhar Pramanick | 2001-04-24 |
| 6218711 | Raised source/drain process by selective sige epitaxy | — | 2001-04-17 |
| 6213869 | MOSFET-type device with higher driver current and lower steady state power dissipation | John C. Holst | 2001-04-10 |
| 6214681 | Process for forming polysilicon/germanium thin films without germanium outgassing | — | 2001-04-10 |
| 6214654 | Method for forming super-steep retrograded channel (SSRC) for CMOS transistor using rapid laser annealing to reduce thermal budget | — | 2001-04-10 |
| 6200869 | Method of fabricating an integrated circuit with ultra-shallow source/drain extensions | Ming-Ren Lin | 2001-03-13 |
| 6194748 | MOSFET with suppressed gate-edge fringing field effect | — | 2001-02-27 |
| 6190980 | Method of tilted implant for pocket, halo and source/drain extension in ULSI dense structures | Ming-Ren Lin, Emi Ishida | 2001-02-20 |
| 6190952 | Multiple semiconductor-on-insulator threshold voltage circuit | Qi Xiang | 2001-02-20 |
| 6187642 | Method and apparatus for making mosfet's with elevated source/drain extensions | Judy Xilin An | 2001-02-13 |
| 6184097 | Process for forming ultra-shallow source/drain extensions | — | 2001-02-06 |
| 6180468 | Very low thermal budget channel implant process for semiconductors | Emi Ishida, Scott Luning, Timothy Thurgate | 2001-01-30 |
| 6180499 | Method for forming polysilicon-germanium gate in CMOS transistor and device made thereby | — | 2001-01-30 |
| 6180476 | Dual amorphization implant process for ultra-shallow drain and source extensions | — | 2001-01-30 |
| 6165849 | Method of manufacturing mosfet with differential gate oxide thickness on the same IC chip | Judy Xilin An | 2000-12-26 |
| 6127216 | Heavily-doped polysilicon/germanium thin film formed by laser annealing | — | 2000-10-03 |
| 6114206 | Multiple threshold voltage transistor implemented by a damascene process | — | 2000-09-05 |
| 6107667 | MOS transistor with low-k spacer to suppress capacitive coupling between gate and source/drain extensions | Judy Xilin An, Yowjuang W. Liu | 2000-08-22 |
| 6100120 | Method of locally forming a high-k dielectric gate insulator | — | 2000-08-08 |