AH

Angela T. Hui

AM AMD: 101 patents #29 of 9,279Top 1%
SL Spansion Llc.: 58 patents #2 of 769Top 1%
Cypress Semiconductor: 11 patents #166 of 1,852Top 9%
Fujitsu Limited: 10 patents #3,161 of 24,456Top 15%
Globalfoundries: 4 patents #817 of 4,424Top 20%
Infineon Technologies Ag: 2 patents #3,160 of 7,486Top 45%
FA Fasl: 2 patents #14 of 52Top 30%
FL Fujitsu Semiconductor Limited: 1 patents #612 of 1,301Top 50%
FL Fujitsu Amd Semiconductor Limited: 1 patents #14 of 40Top 35%
📍 Fremont, CA: #33 of 9,298 inventorsTop 1%
🗺 California: #906 of 386,348 inventorsTop 1%
Overall (All Time): #5,603 of 4,157,543Top 1%
157
Patents All Time

Issued Patents All Time

Showing 126–150 of 157 patents

Patent #TitleCo-InventorsDate
6465835 Charge gain/charge loss junction leakage prevention for flash technology by using double isolation/capping layer between lightly doped drain and gate Tuan Pham, Mark T. Ramsbey, Sameer Haddad 2002-10-15
6461973 Method for forming high quality multiple thickness oxide layers by reducing descum induced defects Jusuke Ogura 2002-10-08
6461951 Method of forming a sidewall spacer to prevent gouging of device junctions during interlayer dielectric etching including silicide growth over gate spacers Paul R. Besser, Yowjuang W. Liu 2002-10-08
6461923 Sidewall spacer etch process for improved silicide formation Paul R. Besser, Susan H. Chen 2002-10-08
6455373 Semiconductor device having gate edges protected from charge gain/loss Tuan Pham, Mark T. Ramsbey, Sameer Haddad, Yu Sun, Chi Chang 2002-09-24
6448608 Capping layer Tuan Pham, Mark T. Ramsbey, Sameer Haddad 2002-09-10
6445051 Method and system for providing contacts with greater tolerance for misalignment in a flash memory Mark S. Chang, Hao Fang, King Wai Kelwin Ko, John Jianshi Wang, Michael K. Templeton +1 more 2002-09-03
6444539 Method for producing a shallow trench isolation filled with thermal oxide Yu Sun, Yue-Song He, Tatsuya Kajita, Mark S. Chang, Chi Chang +1 more 2002-09-03
6444530 Process for fabricating an integrated circuit with a self-aligned contact Hung-Sheng Chen, Unsoon Kim, Yu Sun, Chi Chang, Mark T. Ramsbey +4 more 2002-09-03
6431182 Plasma treatment for polymer removal after via etch Mohammad R. Rakhshandehroo, Mark S. Chang 2002-08-13
6432618 Method for forming high quality multiple thickness oxide layers by reducing descum induced defects Jusuke Ogura 2002-08-13
6420752 Semiconductor device with self-aligned contacts using a liner oxide layer Minh Van Ngo, Yu Sun, Fei Wang, Mark T. Ramsbey, Chi Chang +1 more 2002-07-16
6400030 Self-aligning vias for semiconductors Fei Wang, Robin Cheung, Mark S. Chang, Richard J. Huang 2002-06-04
6391729 Shallow trench isolation formation to eliminate poly stringer with controlled step height and corner rounding 2002-05-21
6369416 Semiconductor device with contacts having a sloped profile Tuan Pham, Mark T. Ramsbey, Yu Sun 2002-04-09
6342415 Method and system for providing reduced-sized contacts in a semiconductor device Tuan Pham, Mark T. Ramsbey, Yu Sun 2002-01-29
6291296 Method for removing anti-reflective coating layer using plasma etch process before contact CMP Wenge Yang, Kashmir Sahota, Mark T. Ramsbey, Suzette K. Pangrle, Minh Van Ngo 2001-09-18
6248627 Method for protecting gate edges from charge gain/loss in semiconductor device Tuan Pham, Mark T. Ramsbey, Sameer Haddad, Yu Sun, Chi Chang 2001-06-19
6242306 Dual bit isolation scheme for flash memory devices having polysilicon floating gates Tuan Pham 2001-06-05
6236091 Method of forming a local interconnect with improved etch selectivity of silicon dioxide/silicide Minh Van Ngo 2001-05-22
6232646 Shallow trench isolation filled with thermal oxide Yu Sun, Yue-Song He, Tatsuya Kajita, Mark S. Chang, Chi Chang +1 more 2001-05-15
6204136 Post-spacer etch surface treatment for improved silicide formation Simon S. Chan, Minh Van Ngo, Paul R. Besser 2001-03-20
6171919 MOS Transistor formation process including post-spacer etch surface treatment for improved silicide formation Paul R. Besser, Minh Van Ngo, Simon S. Chan 2001-01-09
6137126 Method to reduce gate-to-local interconnect capacitance using a low dielectric constant material for LDD spacer Steven C. Avanzino, Minh Van Ngo, Chun Jiang, Hamid Partovi 2000-10-24
6136649 Method for removing anti-reflective coating layer using plasma etch process after contact CMP Wenge Yang, Kashmir Sahota, Mark T. Ramsbey, Suzette K. Pangrle, Minh Van Ngo 2000-10-24