Issued Patents All Time
Showing 151–157 of 157 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6124201 | Method for manufacturing semiconductors with self-aligning vias | Fei Wang, Robin Cheung, Mark S. Chang, Richard J. Huang | 2000-09-26 |
| 6103593 | Method and system for providing a contact on a semiconductor device | Hung-Sheng Chen, Unsoon Kim | 2000-08-15 |
| 5998301 | Method and system for providing tapered shallow trench isolation structure profile | Tuan Pham, Kashmir Sahota | 1999-12-07 |
| 5981341 | Sidewall spacer for protecting tunnel oxide during isolation trench formation in self-aligned flash memory core | Unsoon Kim, Yowjuang W. Liu, Yu Sun | 1999-11-09 |
| 5907781 | Process for fabricating an integrated circuit with a self-aligned contact | Hung-Sheng Chen, Unsoon Kim, Yu Sun, Chi Chang, Mark T. Ramsbey +4 more | 1999-05-25 |
| 5635423 | Simplified dual damascene process for multi-level metallization and interconnection structure | Richard J. Huang, Robin Cheung, Mark S. Chang, Ming-Ren Lin | 1997-06-03 |
| 5468340 | Highly selective high aspect ratio oxide etch method and products made by the process | Subhash Gupta, Susan H. Chen | 1995-11-21 |