Issued Patents 2023
Showing 1–25 of 40 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11830933 | Gate-all-around integrated circuit structures having depopulated channel structures using bottom-up oxidation approach | Gilbert Dewey, Jack T. Kavalieros, Aaron D. Lilak, Patrick Morrow, Anh Phan +2 more | 2023-11-28 |
| 11798991 | Amorphization and regrowth of source-drain regions from the bottom-side of a semiconductor assembly | Aaron D. Lilak, Rishabh Mehandru, Harold W. Kennel, Tahir Ghani | 2023-10-24 |
| 11784239 | Subfin leakage suppression using fixed charge | Sean T. Ma, Aaron D. Lilak, Justin R. Weber, Harold W. Kennel, Gilbert Dewey +5 more | 2023-10-10 |
| 11776898 | Sidewall interconnect metallization structures for integrated circuit devices | Aaron D. Lilak, Anh Phan, Gilbert Dewey, Patrick Morrow | 2023-10-03 |
| 11777013 | Channel formation for three dimensional transistors | Abhishek A. Sharma, Van H. Le, Jack T. Kavalieros, Gilbert Dewey, Matthew V. Metz | 2023-10-03 |
| 11764104 | Forming an oxide volume within a fin | Cheng-Ying Huang, Gilbert Dewey, Jack T. Kavalieros, Aaron D. Lilak, Ehren Mannebach +3 more | 2023-09-19 |
| 11764282 | Antiferroelectric gate dielectric transistors and their methods of fabrication | Ravi Pillarisetty, Brian S. Doyle, Abhishek A. Sharma, Prashant Majhi, Jack T. Kavalieros +1 more | 2023-09-19 |
| 11764275 | Indium-containing fin of a transistor device with an indium-rich core | Chandra S. Mohapatra, Glenn A. Glass, Harold W. Kennel, Anand S. Murthy, Gilbert Dewey +4 more | 2023-09-19 |
| 11764263 | Gate-all-around integrated circuit structures having depopulated channel structures using multiple bottom-up oxidation approaches | Ehren Mannebach, Anh Phan, Aaron D. Lilak, Gilbert Dewey, Cheng-Ying Huang +3 more | 2023-09-19 |
| 11756998 | Source-channel junction for III-V metal-oxide-semiconductor field effect transistors (MOSFETs) | Cheng-Ying Huang, Tahir Ghani, Jack T. Kavalieros, Anand S. Murthy, Harold W. Kennel +4 more | 2023-09-12 |
| 11742346 | Interconnect techniques for electrically connecting source/drain regions of stacked transistors | Aaron D. Lilak, Gilbert Dewey, Cheng-Ying Huang, Christopher J. Jezewski, Ehren Mannebach +4 more | 2023-08-29 |
| 11721735 | Thin film transistors having U-shaped features | Gilbert Dewey, Aaron D. Lilak, Van H. Le, Abhishek A. Sharma, Tahir Ghani +6 more | 2023-08-08 |
| 11699704 | Monolithic integration of a thin film transistor over a complimentary transistor | Van H. Le, Marko Radosavljevic, Han Wui Then, Ravi Pillarisetty, Abhishek A. Sharma +2 more | 2023-07-11 |
| 11695081 | Channel layer formation for III-V metal-oxide-semiconductor field effect transistors (MOSFETs) | Sean T. Ma, Nicholas G. Minutillo, Cheng-Ying Huang, Tahir Ghani, Jack T. Kavalieros +4 more | 2023-07-04 |
| 11676966 | Stacked transistors having device strata with different channel widths | Gilbert Dewey, Jack T. Kavalieros, Cheng-Ying Huang, Matthew V. Metz, Kimin Jun +4 more | 2023-06-13 |
| 11677003 | Nanowire transistor fabrication with hardmask layers | Seung Hoon Sung, Seiyon Kim, Kelin J. Kuhn, Jack T. Kavalieros | 2023-06-13 |
| 11670682 | FINFET transistor having a doped sub fin structure to reduce channel to substrate leakage | Gilbert Dewey, Matthew V. Metz, Anand S. Murthy, Chandra S. Mohapatra, Tahir Ghani +2 more | 2023-06-06 |
| 11664377 | Forksheet transistor architectures | Aaron D. Lilak, Rishabh Mehandru, Ehren Mannebach, Patrick Morrow | 2023-05-30 |
| 11664373 | Isolation walls for vertically stacked transistor structures | Aaron D. Lilak, Patrick Morrow, Gilbert Dewey, Rishabh Mehandru | 2023-05-30 |
| 11659722 | Thin-film-transistor based complementary metal-oxide-semiconductor (CMOS) circuit | Prashant Majhi, Ravi Pillarisetty, Elijah V. Karpov, Brian S. Doyle, Anup Pancholi +1 more | 2023-05-23 |
| 11658208 | Thin film transistors for high voltage applications | Abhishek A. Sharma, Van H. Le, Gilbert Dewey, Ravi Pillarisetty | 2023-05-23 |
| 11652606 | Advanced encryption standard semiconductor devices fabricated on a stacked-substrate | Abhishek A. Sharma, Ravi Pillarisetty, Gilbert Dewey, Jack T. Kavalieros | 2023-05-16 |
| 11646352 | Stacked source-drain-gate connection and process for forming such | Ehren Mannebach, Aaron D. Lilak, Hui Jae Yoo, Patrick Morrow, Anh Phan +2 more | 2023-05-09 |
| 11640961 | III-V source/drain in top NMOS transistors for low temperature stacked transistor contacts | Gilbert Dewey, Ravi Pillarisetty, Jack T. Kavalieros, Aaron D. Lilak, Rishabh Mehandru +6 more | 2023-05-02 |
| 11631717 | 3D memory array with memory cells having a 3D selector and a storage component | Charles C. Kuo, Prashant Majhi, Abhishek A. Sharma | 2023-04-18 |