Issued Patents 2023
Showing 25 most recent of 32 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11849572 | 3D 1T1C stacked DRAM structure and method to fabricate | Sean T. Ma, Abhishek A. Sharma | 2023-12-19 |
| 11830933 | Gate-all-around integrated circuit structures having depopulated channel structures using bottom-up oxidation approach | Willy Rachmady, Gilbert Dewey, Jack T. Kavalieros, Patrick Morrow, Anh Phan +2 more | 2023-11-28 |
| 11798991 | Amorphization and regrowth of source-drain regions from the bottom-side of a semiconductor assembly | Rishabh Mehandru, Willy Rachmady, Harold W. Kennel, Tahir Ghani | 2023-10-24 |
| 11798838 | Capacitance reduction for semiconductor devices based on wafer bonding | Ehren Mannebach, Rishabh Mehandru, Hui Jae Yoo, Patrick Morrow, Kevin Lin | 2023-10-24 |
| 11784239 | Subfin leakage suppression using fixed charge | Sean T. Ma, Justin R. Weber, Harold W. Kennel, Willy Rachmady, Gilbert Dewey +5 more | 2023-10-10 |
| 11776898 | Sidewall interconnect metallization structures for integrated circuit devices | Anh Phan, Gilbert Dewey, Willy Rachmady, Patrick Morrow | 2023-10-03 |
| 11769814 | Device including air gapping of gate spacers and other dielectrics and process for providing such | Ehren Mannebach, Hui Jae Yoo, Patrick Morrow, Kevin Lin, Tristan A. Tronic | 2023-09-26 |
| 11764263 | Gate-all-around integrated circuit structures having depopulated channel structures using multiple bottom-up oxidation approaches | Ehren Mannebach, Anh Phan, Willy Rachmady, Gilbert Dewey, Cheng-Ying Huang +3 more | 2023-09-19 |
| 11764104 | Forming an oxide volume within a fin | Cheng-Ying Huang, Gilbert Dewey, Jack T. Kavalieros, Ehren Mannebach, Patrick Morrow +3 more | 2023-09-19 |
| 11742346 | Interconnect techniques for electrically connecting source/drain regions of stacked transistors | Gilbert Dewey, Cheng-Ying Huang, Christopher J. Jezewski, Ehren Mannebach, Rishabh Mehandru +4 more | 2023-08-29 |
| 11721735 | Thin film transistors having U-shaped features | Gilbert Dewey, Van H. Le, Abhishek A. Sharma, Tahir Ghani, Willy Rachmady +6 more | 2023-08-08 |
| 11721554 | Stress compensation for wafer to wafer bonding | Anant H. JAHAGIRDAR, Chytra Pawashe, Myra McDonnell, Brennen Mueller, Mauro J. Kobrinsky | 2023-08-08 |
| 11699637 | Vertically stacked transistor devices with isolation wall structures containing an electrical conductor | Anh Phan, Patrick Morrow, Stephanie A. Bojarski | 2023-07-11 |
| 11676966 | Stacked transistors having device strata with different channel widths | Gilbert Dewey, Jack T. Kavalieros, Willy Rachmady, Cheng-Ying Huang, Matthew V. Metz +4 more | 2023-06-13 |
| 11672133 | Vertically stacked memory elements with air gap | Patrick Morrow, Hui Jae Yoo, Sean T. Ma, Scott B. Clendenning, Abhishek A. Sharma +2 more | 2023-06-06 |
| 11664377 | Forksheet transistor architectures | Rishabh Mehandru, Ehren Mannebach, Patrick Morrow, Willy Rachmady | 2023-05-30 |
| 11664373 | Isolation walls for vertically stacked transistor structures | Patrick Morrow, Gilbert Dewey, Willy Rachmady, Rishabh Mehandru | 2023-05-30 |
| 11658072 | Vertically stacked transistors in a fin | Sean T. Ma, Justin R. Weber, Patrick Morrow, Rishabh Mehandru | 2023-05-23 |
| 11658221 | Backside contact structures and fabrication for metal on both sides of devices | Patrick Morrow, Rishabh Mehandru, Kimin Jun | 2023-05-23 |
| 11658183 | Metallization structures under a semiconductor device layer | Rishabh Mehandru, Patrick Morrow, Stephen M. Cea | 2023-05-23 |
| 11646352 | Stacked source-drain-gate connection and process for forming such | Ehren Mannebach, Hui Jae Yoo, Patrick Morrow, Anh Phan, Willy Rachmady +2 more | 2023-05-09 |
| 11640961 | III-V source/drain in top NMOS transistors for low temperature stacked transistor contacts | Gilbert Dewey, Ravi Pillarisetty, Jack T. Kavalieros, Willy Rachmady, Rishabh Mehandru +6 more | 2023-05-02 |
| 11616056 | Vertical diode in stacked transistor architecture | Patrick Morrow, Anh Phan, Cheng-Ying Huang, Rishabh Mehandru, Gilbert Dewey +1 more | 2023-03-28 |
| 11616060 | Techniques for forming gate structures for transistors arranged in a stacked configuration on a single fin structure | Gilbert Dewey, Willy Rachmady, Rami Hourani, Stephanie A. Bojarski, Rishabh Mehandru +2 more | 2023-03-28 |
| 11605556 | Back side processing of integrated circuit structures to form insulation structure between adjacent transistor structures | Rishabh Mehandru, Patrick Morrow | 2023-03-14 |